Samsung Electronics Co., Ltd.

Samsung Sdi Co., Inc.

Jong-ho Lee

Nae-in Lee

Hyung-suk Jung

Hyung-cheol Shin

Yun-Seok Kim

Seok-Joo Doh

Sang-yeon Han

Jae-Myung Kim

Yeun-bae Kim

So-Ra Lee

Deok-Hyun Kim

Kyu-Nam Joo

Cha-Young Yoo

Beom-Kwon Kim

Young-Su Kim

Gu-Hyun Chung

In-seon Park

Yong-Mi Yu

Vladimir Skvortsov

An apparatus and method for providing content is provided, which performs a web service initialization through a provided local offline web server and manages a plurality of content provided through a multithreaded web service. The apparatus for providing content includes a communication unit receiving one or more sets of content; a thread creation unit creating one or more threads that are given to the content to process a work; and a page creation unit having a frame per thread and creating an image page for playing the content on a web browser.

Apparatus and method for providing content

A lithium titanium oxide for an anode active material of a lithium rechargeable battery, wherein a X-ray diffraction (XRD) spectrum has a first peak of LiTiOand a second peak, and A/Ais in a predetermined range, as a result of XRD analysis, where Ais an Area of the first peak and Ais an Area of the second peak in XRD.

Lithium titanium oxide for anode active material for lithium rechargeable battery, method of preparing lithium titanium oxide, and lithium rechargeable battery including lithium titanium oxide

High dielectric layers formed from layers of hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide, and/or other metal oxides and silicates disposed on silicon substrates or ozone oxide layers over silicon substrates may be nitrided and post thermally treated by oxidation, annealing, or a combination of oxidation and annealing to form high dielectric layers having superior mobility and interfacial characteristics.

Post thermal treatment methods of forming high dielectric layers over interfacial layers in integrated circuit devices

Field effect transistors include a semiconductor substrate having a channel region of first conductivity type therein extending adjacent a surface thereof. Source and drain regions of second conductivity type are also provided at opposite ends of the channel region. The source and drain regions extend in the semiconductor substrate and form P-N rectifying junctions with the channel region. A gate electrode extends on the channel region and comprises a first electrically conductive material having a first work function. A first sub-gate electrode extends on the channel region and comprises a second electrically conductive material having a second work function that is unequal to the first work function. The second electrically conductive material is preferably selected so that a difference between the second work function and a work function of the channel region is sufficient to form an inversion-layer in a portion of the channel region extending opposite the first sub-gate electrode when the first sub-gate electrode is at a zero potential bias relative to the channel region.

Methods of forming and operating field effect transistors having gate and sub-gate electrodes

Field effect transistors having gate and sub-gate electrodes that utilize different work function materials and methods of forming same

A semiconductor memory device, a method for manufacturing the same, a memory circuit including the semiconductor memory device, and a method for driving the same, are provided. In detail, one transistor forms a memory cell, and a single transistor cell capable of arbitrarily accessing the memory cell, a method for manufacturing the same, a memory circuit, and a method for driving the memory circuit, are provided. An island type semiconductor layer as an active region is formed on a ferroelectric layer. A word line crosses the semiconductor layer. A source is formed on the semiconductor layer on one side of the word line, and a drain is formed on the other side. A plate line is formed below the ferroelectric layer to face the word line, and intersects the word line. A drive line is connected to the source, and a bit line is connected to the drain.

Single transistor cell, method for manufacturing the same, memory circuit composed of single transistors cells, and method for driving the same

Single transistor cell, method for manufacturing the same, memory circuit composed of single transistor cells, and method for driving the same

A ferroelectric memory device includes a silicon-on-insulator substrate having a handling wafer, a first insulating layer, and a semiconductor layer. It also includes a first conductive layer used as a bit line formed in the first insulating layer, a source region formed in the semiconductor layer, a drain region formed in the semiconductor layer, a second insulating layer formed over the semiconductor layer between the source and drain regions, a second conductive layer for use as both a lower electrode and gate electrode, formed over the second insulating layer between the source and drain regions, a ferroelectric layer formed over the semiconductor layer, and a third conductive layer for use as an upper electrode formed over the ferroelectric layer. For reading, writing, and erasing, different voltages are applied to the upper electrode and the semiconductor layer between the drain and source. For writing, the upper electrode receives a writing voltage, and the semiconductor layer receives a ground voltage. This brings the drain and source to a floating state to either invert polarization of the ferroelectric layer or retain initial polarization, depending upon the data. For erasing, the upper electrode receives an erasing voltage, and the semiconductor layer receives a ground voltage. This brings the drain and source to a floating state. For reading, the upper electrode receives a reading voltage, and the semiconductor layer receives a ground voltage. A sensing current is then provided to the drain, and potential variation is sensed on the bit line.

Nonvolatile semiconductor memory device, a method of fabricating the

A touch screen input apparatus including a plurality of touch screens, a chip mounter provided with the apparatus, and a method for controlling the chip mounter are provided which improve the capability of controlling the chip mounter. The touch screen input apparatus of a chip mounter comprises a plurality of monitors dispersedly disposed in the vicinity of the chip mounter to provide display screens for inputting the letter or numeral, a touch panel attached to each monitor for recognizing a touched coordinate on each display screen and outputting an electrical signal, priority order and release time controlling means for receiving the signals output from the touch panels and recognizing the order of generation thereof, and a multiplexer for receiving the signals output from the touch panels and sequentially selecting and outputting the input signals according to the order recognized by the priority order and release time controlling means. The touch screen input apparatus includes the monitors and the touch screen which are located at different places in order to control the chip mounter, thereby improving the operational capability of the chip mounter.

Touch screen input apparatus for chip mounter, chip mounter including

Growing community of inventors

Yongin-si, South Korea

Jong-ho Lee