Skhynix Inc.

Hynix Semiconductor Inc.

Ace Technologies Corporation

Jong-Ho Jung

Byong-Nam Kim

Byoung-Nam Kim

Seung-Cheol Lee

A memory module includes a plurality of memory devices; a plurality of data buffers suitable for exchanging data with a memory controller; and a module controller suitable for transferring the data between the memory devices and the data buffers based on a command, an address and a clock provided from the memory controller, calculating delay times for transferring the data according to locations of the data buffers, and controlling times at which the data are transferred based on the calculated delay times.

Memory module and memory system including the same

A broadband internal antenna using double electromagnetic coupling is disclosed. The disclosed antenna may include: a first conducting member electrically connected to a feeding point; a second conducting member placed at a designated distance from at least a portion of the first conducting member so as to allow a first electromagnetic coupling with at least a portion of the first conducting member, and remaining in a floating state without being coupled to a ground and the feeding point; a third conducting member placed at a designated distance from the second conducting member so as to allow a second electromagnetic coupling with the second conducting member, and electrically connected to the ground; and a fourth conducting member extending from the third conducting member, for radiating RF signals. The disclosed antenna has the advantage of providing broadband characteristics within a limited size.

Broadband built-in antenna using a double electromagnetic coupling

A semiconductor memory device includes a delay locked loop configured to generate a delay locked loop (DLL) clock signal by delaying an external clock signal by a first delay time and generate a feedback clock signal by delaying the DLL clock signal by the second delay time, wherein the first delay time corresponds to a phase difference between the external clock signal and the feedback clock signal and an output enable control circuit configured to generate an output enable signal in response to CAS latency information and the first and second delay times after the delay locked loop performs a locking operation.

Semiconductor memory device and operation method thereof

An integrated circuit of a multiple die package structure having a plurality of semiconductor devices, each of the plurality of semiconductor devices may include an active termination circuit configured to perform an active termination operation to the semiconductor device, and to be turned off in a disable state of an active termination setting code, a multiple die package information transfer unit configured to transfer a multiple die package information signal, and a compulsory termination unit configured to selectively convert the active termination setting code into the disable state in response to the multiple die package information signal.

Integrated circuit and operation method thereof

An internal antenna for attaching to a terminal housing is disclosed. The antenna includes: a perpendicular structure formed in a perpendicular direction to a substrate and positioned in contact with an inner wall of a housing; a first conductive member electrically connected to a power feed and joined to the perpendicular structure to extend in a perpendicular direction to the substrate; and a second conductive member electrically connected to a ground, joined to the perpendicular structure, and separated by a particular distance from the first conductive member to extend in a perpendicular direction to the substrate. The first conductive member is joined to the inner wall of the housing to extend in a first direction orthogonal to the perpendicular direction, and the second conductive member is joined to the inner wall of the housing to extend in the first direction at a particular distance from the first conductive member.

Internal antenna joined to terminal housing

A synchronous semiconductor device includes an internal command generation unit configured to generate an internal command corresponding to a source command, a delay locked loop configured to delay a source clock by a first delay time required for delay-locking to generate a delay locked clock, a delay time determination unit configured to determine a second delay time for delay-locking the internal command using the source clock, the second delay time being determined by reflecting a third delay time generated on a command path, and a latency control unit configured to shift the internal command by a shifting period, in which the second delay time is reflected, in response to the delay locked clock.

Synchronous semiconductor device having delay locked loop for latency control

The semiconductor device includes a termination control unit configured to generate a termination enable signal and termination resistance information in response to termination activation information, dynamic activation information, normal resistance information, and dynamic resistance information wherein the termination enable signal is activated when a delay lock loop is inactivated, and a termination unit configured to be controlled in response to the termination enable signal and terminate an interface pad by using a resistance value determined by the termination resistance information.

Termination control circuit and semiconductor device including the same

An on die thermal sensor includes a bandgap unit for generating a first voltage containing temperature information, a tracking unit for tracking a voltage level of the first voltage, and a low power control unit for generating a tracking enable signal for enabling the tracking unit and disabling the tracking unit after a minimum tracking operation time of the tracking unit elapses.

Growing community of inventors

Gyeonggi-do, South Korea

Jong-Ho Jung