Hynix Semiconductor Inc.

Skhynix Inc.

Ypp Co., Ltd.

Jong Han Shin

Hyung Soon Park

Sung Jun Kim

Jum Yong Park

Sang Ick Lee

Jae Hyun Kim

Young Ju Lee

Cheol Hwi Ryu

Yong Gil Kim

Provided are a triple redundant digital protective relay and an operating method therefor. The triple redundant digital protective relay according to the present invention includes: three power monitoring control devices which have a triple redundant structure and control a circuit breaker for separating a failed power system based on a 2 out of 3 voting using real-time mutual data communication; and a central communication device which acquires data related to an operating state of the power system from the three power monitoring control devices and manages the acquired data related to the operating state of the power system.

Triple redundant digital protective relay and operating method therefor

A phase-change random access memory device includes a semiconductor substrate, a bottom electrode structure formed on the semiconductor substrate, a cylindrical bottom electrode contact that includes a conductive material layer, which is in contact with the bottom electrode, and a cylindrical phase-change material layer that is in contact with the bottom electrode contact. Therefore, the contact area between the bottom electrode contact and the phase-change material layer can be minimized.

Phase-change random access memory device and method of manufacturing the same

A semiconductor device having vertically aligned transistors made from pillar structures that have flat side surfaces is presented. The semiconductor device includes a semiconductor substrate, spacers, and gates. The semiconductor substrate has pillar structures that have flat side surfaces. The spacers are on sidewalls only on the upper portions of the pillar structures. The gates surround lower portions of the pillar structures.

Semiconductor device having vertically aligned pillar structures that have flat side surfaces and method for manufacturing the same

A method for manufacturing a semiconductor device having a vertical transistor includes forming hard masks on a semiconductor substrate to expose portions of the semiconductor substrate. Then the exposed portions of the semiconductor substrate are etched to define grooves in the semiconductor substrate. A gate conductive layer is formed on the hard masks and surfaces of the grooves to a thickness that does not completely fill the grooves. A sacrificial layer is formed on the gate conductive layer to completely fill the grooves. A partial thickness of the sacrificial layer is removed to expose the gate conductive layer and portions of the gate conductive layer formed on the hard masks and on sidewalls of upper portions of the grooves are removed. The remaining sacrificial layer is completely removed. Gates are formed on sidewalls of lower portions of the grooves by etching the gate conductive layer.

Method for manufacturing semiconductor device having vertical transistor

Disclosed is a method of manufacturing a semiconductor device. The method includes the steps of forming gates on a substrate, forming junction areas on a surface of the substrate, forming a first BPSG layer on a resultant structure of the substrate, performing a first CVD process for the first BPSG layer, forming a second BPSG layer on the first BPSG layer, forming a landing plug contact, depositing a polysilicon layer on a resultant structure of the substrate, and performing a second CMP process for the polysilicon layer, the second BPSG layer and the nitride hard mask. The CMP processes are carried by using acid slurry having a high polishing selectivity with respect to the nitride layer, so a step difference between the cell region and the peripheral region is removed, thereby simplifying the semiconductor manufacturing process and removing a dishing phenomenon.

Method of manufacturing semiconductor device

The present invention discloses method for manufacturing capacitor of semiconductor device wherein a bonding layer is exposed via etch-back process without using a contact hole mask. In accordance with the method of the present invention, an interlayer insulating film, a bonding layer and a hard mask layer are sequentially formed on a semiconductor substrate. The hard mask layer, the bonding layer and the interlayer insulating film are then etched to form a storage electrode contact hole. The storage electrode contact hole is partially filled to form a storage electrode contact plug and the remaining portion is filled with a barrier metal layer pattern. The hard mask layer is then removed and a storage electrode contacting the barrier metal layer pattern is then formed on the bonding layer.

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Seoul, South Korea

Jong Han Shin