Skhynix Inc.

Hynix Semiconductor Inc.

Jong-Han Shin

Jum-Yong Park

Ki-Seon Park

Ga-Young Ha

Cheol-Hwi Ryu

Sung-Jun Kim

Seok-Pyo Song

Sung-Woong Chung

Hyung-Soon Park

Myung-Ok Kim

Jeong-Myeong Kim

Chi-Ho Kim

Noh-Jung Kwak

Dong-Sun Sheen

Sang-Tae Ahn

Kyung-Bo Kim

Bo-Kyung Jung

Bo-Min Park

An electronic device including a semiconductor memory. The semiconductor memory may include a variable resistance element. The variable resistance element may include a first magnetic layer formed over a first auxiliary layer, a tunnel barrier layer formed over the first magnetic layer, a second magnetic layer formed over the tunnel barrier layer, a second auxiliary layer formed over the second magnetic layer, and a hard mask formed over the second auxiliary layer. Side surfaces of the first magnetic layer may be substantially aligned with side surfaces of the first auxiliary layer, and the side surfaces of the first magnetic layer may deviate from side surfaces of the hard mask.

Electronic device and method for fabricating the same

A method for fabricating an electronic device including a semiconductor memory includes: forming a variable resistance element over a substrate, the variable resistance element including a metal-containing layer and an MTJ (Magnetic Tunnel Junction) structure which is located over the metal-containing layer and includes a free layer having a variable magnetization direction, a pinned layer having a fixed magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer; forming an initial spacer containing a metal over the variable resistance element; performing an oxidation process to transform the initial spacer into a middle spacer including an insulating metal oxide; and performing a treatment using a gas or plasma including nitrogen and hydrogen to transform the middle spacer produced by the oxidation process into a final spacer including an insulating metal nitride or an insulating metal oxynitride.

Electronic device and method for fabricating the same using treatment with nitrogen and hydrogen

A method for fabricating an electronic device including a semiconductor memory includes: forming an etching target layer over a substrate; forming an initial hard mask pattern including a carbon-containing material over the etching target layer; forming a hard mask pattern by doping an impurity which increases a hardness of the carbon-containing material into a surface portion of the initial hard mask pattern; and etching the etching target layer by using the hard mask pattern as an etching barrier.

An electronic device includes a transistor. The transistor includes: a substrate including an active region that extends in a first direction; a gate structure disposed in the substrate and crossing the active region in a second direction that crosses the first direction; recesses disposed in the active region on two sides of the gate structure in the first direction, a center of a bottom surface of a first recess being more depressed in a third direction than two edges of the bottom surface along the first direction, the third direction being perpendicular to the first and second directions; an insulating layer disposed in the first recess; and a junction layer disposed over the insulating layer in the first recess in the third direction, a top surface of the insulating layer being below the two edges of the bottom surface and having a smaller curvature than the bottom surface.

Electronic device including transistor and method for fabricating the same

A method for fabricating an electronic device that includes a metal-insulator-semiconductor (M-I-S) structure includes: providing a semiconductor layer; forming a primary insulation layer of a first thickness over the semiconductor layer; forming a reactive metal layer of a second thickness over the primary insulation layer, where the second thickness is greater than the first thickness; forming a primary capping layer of a third thickness over the reactive metal layer, where the third thickness is greater than the second thickness; and performing a thermal treatment.

Electronic device including metal-insulator-semiconductor structure and method for fabricating the same

A semiconductor device includes a substrate having a cell region and a peripheral region, a buried gate formed over the substrate of the cell region, a peripheral gate formed over the substrate of the peripheral region and comprising a conductive layer, an inter-layer dielectric layer that covers the substrate, and a peripheral bit line formed inside the inter-layer dielectric layer and contacting the conductive layer.

Semiconductor device with buried gates and bit line contacting peripheral gate

Electronic devices having semiconductor elements and methods for fabricating such devices including, a method for fabricating an electronic device including a semiconductor memory, which includes: forming a sacrificial layer on a substrate including a first region and a second region; selectively etching the sacrificial layer and the substrate of the first region to form a trench; forming a first gate that fills a part of the trench in the first region; forming a gate protection layer on the first gate to fill the remaining part of the trench; removing the sacrificial layer of the first region to form a grooved portion surrounded by the gate protection layer; forming a conductive plug to cover the grooved portion; removing the sacrificial layer of the second region; and forming a second gate on the substrate of the second region.

Electronic device having buried gate and method for fabricating the same

Semiconductor device with buried gates and fabrication method thereof

A method for fabricating a semiconductor device includes forming landing plugs over a substrate, forming a trench by etching the substrate between the landing plugs, forming a buried gate to partially fill the trench, forming a gap-fill layer to gap-fill an upper side of the buried gate, forming protruding portions of the landing plugs, and trimming the protruding portions of the landing plugs.

Semiconductor device with buried gate and method for fabricating the same

A semiconductor device includes buried gates formed over a substrate, storage node contact plugs which are formed over the substrate and include a pillar pattern and a line pattern disposed over the pillar pattern, and a bit line structure which is formed over the substrate and isolates adjacent ones of the storage node contact plugs from each other.

A method for fabricating a semiconductor device is provided, the method includes forming a plug conductive layer over an entire surface of a substrate, etching the plug conductive layer to form landing plugs, etching the substrate between the landing plugs to form a trench, forming a gate insulation layer over a surface of the trench and forming a buried gate partially filling the trench over the gate insulation layer.

Method for fabricating buried gates using pre landing plugs

A method for fabricating a semiconductor device includes forming a hard mask pattern over a substrate, forming an isolation layer for defining an active region by using the hard mask pattern, forming a buried gate in and across the active region and the isolation layer over the substrate, forming an inter-layer dielectric layer over the substrate, forming a storage node contact hole that exposes the hard mask pattern by selectively etching the inter-layer dielectric layer, extending the storage node contact hole to expose the active region by removing the hard mask pattern exposed under the storage node contact hole, and forming a storage node contact plug that fills the extended storage node contact hole.

Method for fabricating semiconductor device with buried gate

A method for fabricating a semiconductor device includes sequentially stacking a pad oxide layer and a hard mask layer over a substrate, forming a device isolation layer over the substrate, forming a capping layer pattern configured to open a first region of the substrate and cover a second region of the substrate, removing the hard mask layer, removing the capping layer pattern, and removing the pad oxide layer.

Growing community of inventors

Gyeonggi-do, South Korea

Jong-Han Shin