Samsung Electronics Co., Ltd.

Jong-hak Won

Jae-Woong Lee

Sang-bong Park

A semiconductor memory device having a hierarchical I/O line structure is provided. The semiconductor memory array includes a memory cell array which is divided into a plurality of sub-arrays by sub-word line driver areas and bit line sense amplifier areas; local input/output (I/O) lines which are arranged in the bit line sense amplifier areas; and global I/O lines which are arranged in the sub-word line driver areas, wherein at least one end of each of the local I/O lines is formed in a bit line sense amplifier area. The semiconductor memory device may also have a dummy bit line sense amplifier area capable of dividing local I/O lines in a bit line sense amplifier area, and can reduce the number of sub-word line driver areas such that the chip size can be reduced.

Scalable hierarchical I/O line structure for a semiconductor memory device

A memory device having a memory core, a local equalizer, and a local-global multiplexer. The memory core is connected to local input/output lines and global input/output lines. The local equalizer is configured to precharge the local input/output lines. The global multiplexer is configured to alternately connect and disconnect the local input/output lines with the global input/output lines. The local equalizer is in a same layer of the memory device as the local-global multiplexer.

Memory device having reduced layout area

A memory device having reduced power consumption by minimizing the operation of circuits utilized in reading and writing data, and a data reading and writing method of the memory device, are provided. In the memory device, upon data reading, an input and output sense amplifier amplifies data which is read from a memory cell and transferred to an input and output line, and transfers the resultant data to a data output line. Upon data writing, a writing driver receives write data via a data input line and transfers the received write data to the input and output line. Each of the input and output sense amplifier and the writing driver operates only when previously-read or -written data is different from current data to be read or written.

Memory device having minimized power consumption and data read and write method of the same

A memory test control circuit in an MML integrated circuit is connected to a first pad which receives memory control signals to control first and second memories of the MML circuit. The memory test control circuit is also connected to a second pad which receives memory data signals for the first and second memories. The memory test control circuit is also connected to the logic block and to the first and second memories. The memory test control circuit transmits the memory control signals and the memory data signals to the first and second memories when the first and second memories are tested and transmits the memory control signals and the memory data signals to the logic block during normal operation of the MML integrated circuit. Accordingly, the memory test control circuit allows pass-through of memory data and control signals directly to the memory blocks during test mode, and provides the memory data and control signals to the logic block during normal operations.

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Kyungki-do, South Korea

Jong-hak Won