Samsung Electronics Co., Ltd.

Daegu Gyeongbuk Institute of Science and Technology

Jong-Geon Lee

Jin In So

Prashant Vishwanath Mahendrakar

Vishnu Charan Thummala

Eldho Mathew Pathiyakkara Thombra

Jin Woo Jung

Jinin So

Eldho Pathiyakkara Thombra Mathew

Raghu Vamsi Krishna Talanki

Minho Kim

Kyungsoo Kim

Daehoon Kim

You-Keun Han

Seung-Jin Seo

Seung-Man Shin

Yongsuk Kwon

Kyudong Lee

Jeonghyeon Cho

Jinseong Yun

Hui-chong Shin

Kyung-Hee Han

Archita Khare

Vinod Kumar Srinivasan

Ravi Shankar Venkata Jonnalagadda

Eldho P Mathew

Venkata Ravi Shankar Jonnalagadda

Hyungwon Park

Hwanjun Lee

Minwoo Jang

Yeaji Jung

Memory systems and methods for operating the same. A memory system comprises a first memory, a second memory having an operating speed different from that of the first memory, a storage unit configured to store an instruction, a prefetcher configured to update prefetcher data in response to occurrence of cache hits and a processor configured to execute the instruction stored in the storage unit. When the instruction is executed, the processor is configured to generate prefetcher friendly data by filtering the prefetcher data, set a prefetcher friendly bit in a first pointer area corresponding to the first memory and a second pointer area corresponding to the second memory based on the prefetcher friendly data, and determine whether data of the first pointer area and the second pointer area are migrated, in consideration of a reference bit and the prefetcher friendly bit of the first and second pointer areas.

Memory systems and methods for operating memory systems

A method for operating a Near Memory Processing (NMP) Dual In-line Memory Module (DIMM) for DIMM-to-DIMM communication is provided. The NMP DIMM includes one or more ports for communicative connection to other NMP DIMMs. The method includes parsing, by one NMP DIMM, a NMP command received from a processor of a host platform, identifying data dependencies on one or more other NMP DIMMs based on the parsing, establishing communication with the one or more other NMP DIMMs through one or more ports of the one NMP DIMM, receiving data from the one or more other NMP DIMMs through one or more ports of the one NMP DIMM, processing the NMP command using the data received from one of the one or more other NMP DIMMs and data present in the one NMP DIMM, and sending a NMP command completion notification to the processor of the host platform.

Near memory processing dual in-line memory module and method for operating the same

The present disclosure relates to field of Dual In-Line Memory Modules that discloses method and system for generating memory maps. The method comprises detecting, by computing system, at least one of DIMM and one or more Dynamic Random Access Memory (DRAM) chips associated with computing system. The one or more accelerators are configured in at least one of DIMM and one or more DRAM chips. Further, the method includes determining accelerator information for each of one or more accelerators via at least one of Serial Presence Detect (SPD) and Multi-Purpose Register (MPR) associated with at least one of DIMM and one or more DRAM chips. Method includes generating unique memory map for each of one or more accelerators based on accelerator information of corresponding one or more accelerators. As a result, performance of computing system may be improved as accelerator capabilities of one or more accelerators are effectively utilized.

Method and system for generating memory maps

A Near Memory Processing (NMP) module including: a plurality of memory units; an Input/Output (I/O) interface configured to receive commands from a host system, wherein the host system includes a host memory controller configured to access the plurality of memory units; a decoder configured to decode the commands and generate a trigger; and an NMP memory controller configured to: receive the trigger from the decoder; and generate a signal in response to the trigger to synchronize the NMP module with the host system.

Synchronizing control operations of a near memory processing module with a host system

A Near Memory Processing (NMP) Dual In-line Memory Module (DIMM) is provided that includes random access memory (RAM), a Near-Memory-Processing (NMP) circuit and a first control port. The NMP circuit is for receiving a command from a host system, determining an operation to be performed on the RAM in response to the command, and a location of data within the RAM with respect to the determined operation. The first control port interacts with a second control port of the host system to enable the NMP circuit to exchange control information with the host system in response to the received command.

Near memory processing (NMP) dual in-line memory module (DIMM)

A Near Memory Processing (NMP) dual in-line memory module (DIMM) for managing an address map is provided. The NMP DIMM includes: a static random-access memory (SRAM) provided on a Double Data Rate (DDR) interface; and an address management controller coupled to the SRAM, and configured to control the NMP DIMM to: receive a first indication from a host system to perform interface training for operating an SRAM space; perform the interface training using a first address map based on the first indication; receive a second indication from the host system indicating completion of the interface training for operating the SRAM space; switch from the first address map to a second address map for operating the SRAM space in response based on the second indication; and operate the SRAM space using the second address map.

Method and NMP DIMM for managing address map

A memory module includes a first memory device, a second memory device, and a processing buffer circuit that is connected to the first memory device and the second memory device (independently of each other) and a host. A processing buffer circuit is provided, which includes a processing circuit and a buffer. The processing circuit processes at least one of data received from the host, data stored in the first memory device, or data stored in the second memory device based on a processing command received from the host. The buffer is configured to store data processed by the processing circuit. The processing buffer circuit is configured to communicate with the host in compliance with a DDR SDRAM standard.

Memory modules and methods of operating same

A power management integrated circuit includes first pads, second pads, a third pad, and a fourth pad that are configured to be connected with an external device, a regulation block that receives first voltages from the first pads, converts the first voltages to second voltages, and outputs the second voltages to the second pads, a communication block that receives a command through the third pad and outputs an internal information request received together with the command responsive to the command, and a logic block that controls an operation of the regulation block, receives the internal information request from the communication block, and outputs internal state information to the fourth pad based on the internal information request.

Power management integrated circuits and semiconductor memory modules including power management integrated circuits

Methods and apparatuses for entering at least one memory into a test mode are provided. At least one test MRS bit may be stored in a first register for controlling the memory. At least one test MRS code may be programmed into a second register. Each of the at least one bits stored in the first register may correspond one of the at least one test MRS codes stored in the second register.

Methods and apparatus for interfacing between test system and memory

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Seoul, South Korea

Jong-Geon Lee