Samsung Electronics Co., Ltd.

Jong-Doo Joo

Cheol-ha Lee

Gyu-Hong Kim

Jung-han Kim

Cheol-Ha Lee

Sang-Seok Lee

A one-time programmable (OTP) memory includes an OTP cell array including a plurality of OTP cells that each include a programming transistor configured to change irreversibly when programmed; a temperature compensation reference voltage generating unit configured to sense a temperature of the OTP cell memory and generate a reference voltage such that as the sensed temperature changes, the reference voltage generated by the temperature compensation reference voltage generating unit changes in a manner that is inversely proportional the change in the sensed temperature; and a temperature compensation operating voltage generating unit configured to receive the reference voltage to generate an operating voltage that is proportional to the reference voltage and is applied to the OTP cell array.

One-time programmable memory and system-on chip including one-time programmable memory

An oscillation circuit includes an internal voltage generator and an oscillator. The internal voltage generator receives an external voltage and generates an internal voltage based on the external voltage. The internal voltage varies in linearly with an operational temperature. The oscillator generates a variable oscillation signal based on the internal voltage. A period of the variable oscillation signal varies in linearly with the operational temperature.

Oscillation circuits having temperature-dependent frequency generation and semiconductor memory devices having temperature-dependent self refresh rate

An active charge pump circuit may include a charge pump circuit, a control circuit, and a charge transfer circuit. The charge pump circuit may generate a charge pumping voltage in response to an active enable signal. The control circuit may generate a charge transfer control signal varying between a ground voltage and a boosted power supply voltage that is twice as much as a power supply voltage in response to the active enable signal. The charge transfer circuit may output the charge pumping voltage as an active voltage in response to the charge transfer control signal.

Voltage generating circuit and semiconductor device having the same

A semiconductor memory device includes a memory core and an input/output circuit. The memory core amplifies a signal of a memory cell to output the amplified signal through an input/output line pair in a read mode, receives a signal of the input/output line pair to store in the memory cell in a write mode, and electrically separates a bit line pair from the input/output line pair in response to a read column selection signal, a write column selection signal and a first data masking signal. The input/output circuit buffers and provided a signal of the input/output line pair to input/output pins, receives input data from the input/output pins, and buffers the received input data to provide the buffered input data to the input/output line pair. Thus, the semiconductor device can perform a fast data writing operation.

Semiconductor memory device of controlling bit line sense amplifier

An embedded memory and methods thereof are provided. The example embedded memory may include a first memory block configured to output data, selected by a first column select signal, on a first scan output line if the first memory block is determined to be non-defective and a second memory block configured to output data, selected by a second column select signal on a second scan output line if the first memory block is determined to be non-defective, the second memory block further configured to output data, selected by the first column select signal, on the first scan output line if the first memory block is determined to be defective. A first example method may include performing a memory scan on a plurality of cell arrays, determining whether at least one of a plurality of cell arrays is defective based on the results of the memory scan, receiving data to be stored in a first cell array of the plurality of cell arrays, storing the received data in the first cell array if the determining determines the first cell array not to be defective and storing the received data in a second cell array, if the determining determines the first cell array to be defective. A second example method may include retrieving data from an embedded memory, including receiving data on a first scan output line from a first cell array, included among a plurality of cell arrays, if the first cell array is not defective and receiving data on the first scan line from a second cell array if the first cell array is defective.

Embedded memory and methods thereof

A sense amplifier includes: a bit line and a complementary bit line; a data input/output line and a complementary data input/output line; first and second transistors which are connected in series between the data input/output line and the bit line; and third and fourth transistors which are connected in series between the complementary data input/output line and the complementary bit line, where the gate of the first transistor is connected to the complementary data input/output line, the gate of the third transistor is connected to the data input/output line, and a write column select line enable signal is input to the gates of the second and fourth transistors. Since the sense amplifier can write data before data of adjacent bit line pairs are amplified in a semiconductor memory device, the write timing can be reduced.

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Seongnam-si, South Korea

Jong-Doo Joo