International Rectifier Corporation

Jong-Deog Jeong

Jun Honda

In one embodiment, a method for detecting a load in a switched-mode power converter is provided. The switched-mode power converter includes high and low-side power switches which are configured to be driven respectively by high and low-side drive signals to provide a switching voltage. The high and low-side drive signals include a plurality of dead-time periods. The method includes monitoring a waveform of the switching voltage and at least one of the high and low-side drive signals. The monitored waveform of the switching voltage is compared to the monitored waveform of the at least one of the high and low-side drive signals to determine whether the switching voltage is high or low during at least one of the dead-time periods. A current measurement of the load is determined based on whether the switching voltage is high or low during the at least one of the dead-time periods.

Load detection for switched-mode power converters

A simple, low cost, gate driver and bias circuit provides for a wider operating voltage range exceeding the normal component breakdown voltage of components such as NMOS and PMOS transistors. A CMOS process with an epitaxial layer as bulk and p-type substrate is used to implement the circuit in this example.

Gate driver output stage with bias circuit for high and wide operating voltage range

An integrated high-voltage linear amplifier IC with reduced power dissipation, faster operation, and small die size, comprising a low side well and a floating high side well; an error amplifier for receiving a noise signal; a level shifting circuit in the low side well for outputting a current mode error signal based on the noise signal to the high side well in differential current mode for noise reduction; and a drive circuit in the high side well. A voltage/current converter receives a voltage mode error signal based on the noise signal and supplies the current input signal. Current mirror circuitry and the drive circuit in the high side well outputs a sum current derived from the current mode error signal for driving external power devices.

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Rancho Palos Verdes, CA, United States of America

Jong-Deog Jeong