Electronics and Telecommunications Research Institute

Jong-dae Kim

Sang-gi Kim

Jin-gun Koo

Dae-Yong Kim

Kyoung-Ik Cho

Dae-woo Lee

Tae-moon Roh

A method for manufacturing a trench-gate type power semiconductor device is provided. A drift region having a low concentration of a first conductivity type and a body region of a second conductivity type are formed on a semiconductor substrate having a high concentration of the first conductivity type. A trench is formed using a nitride layer pattern and a sidewall oxide layer formed at sidewalls of the nitride layer pattern as a mask, and then the sidewall oxide layer is removed. The corners of the trench are rounded by performing a heat treatment in a hydrogen atmosphere. A source region having a high concentration of the first conductivity type is formed using the nitride layer pattern as a mask. The nitride layer pattern is removed, and an upper oxide layer pattern is formed to cover a predetermined portion of the source region and the gate conductive layer. A body contact region of the second conductivity type is formed using the upper oxide layer pattern as a mask. A source electrode is formed to be electrically connected to the body contact region, and a drain electrode is formed to be electrically connected to the semiconductor substrate.

Method for manufacturing trench-gate type power semiconductor device

A method for fabricating a semiconductor power integrated circuit includes the steps of forming a semiconductor structure having at least one active region, wherein an active region includes a well region for forming a source and a drift region for forming a drain region, forming a trench for isolation of the active regions, wherein the trench has a predetermined depth from a surface of the semiconductor structure, forming a first TEOS-oxide layer inside the trench and above the semiconductor structure, wherein the first TEOS-oxide layer has a predetermined thickness from the surface of the semiconductor device, forming a second TEOS-oxide layer on the first TEOS-oxide layer, wherein a thickness of the second TEOS-oxide layer is smaller than that of the first TEOS-oxide layer, and performing a selective etching to the first and second TEOS-oxide layers, to thereby simultaneously form a field oxide layer pattern, a diode insulating layer pattern and a gate oxide layer pattern, to thereby reduce processing steps and obtain a low on-resistance.

Semiconductor power integrated circuit

Method for fabricating semiconductor power integrated circuit

Growing community of inventors

Taejon, South Korea

Jong-dae Kim