Electronics and Telecommunications Research Institute

Kwangwoon University Industry-academic Collaboration Foundation

Jong-Dae Kim

Tae-Moon Roh

Jung-Hee Suk

Yil-Suk Yang

Se-Wan Heo

Ik-Jae Chun

Chun-Gi Lyuh

Byoung-Gon Yu

Jong-Hyeok Park

Ho-Gyeong Yun

Hunkyun Pak

Man-Gu Kang

Yong-Seok Jun

Seung-Yup Lee

Hyuk Joo Kim

Kyung-Soo Kim

Hee-Bum Jung

Byung-Doo Kim

In-San Jeon

Jae-Seok Kim

Sang-gi Kim

Dae-woo Lee

Seung-Chul Lee

Soon-Il Yeo

Soo-Young Oh

Il-yong Park

Kwi-Dong Kim

Seong-Won Lee

Dae-Woo Lee

Il-Yong Park

Sung-ku Kwon

Gyu-Hyun Kim

Jong-Ki Kwon

Provided are a dye-sensitized solar cell and a method of fabricating the same. The dye-sensitized solar cell includes an electrode structure including a conductive layer having pores that are regularly arranged, a semiconductor oxide layer disposed on a surface of the conductive layer, and a dye layer disposed on a surface of the semiconductor oxide layer.

Dye-sensitized solar cell and method of fabricating the same

There is provided a system for cleaning a surface of a solar cell panel. The system includes a measurement unit measuring a power generation value of a solar cell panel, a reference unit providing a reference value, a control unit comparing the power generation value measured at the measurement unit with the reference value provided from the reference unit to command cleaning of the solar cell panel, a driving unit operating a cleaning apparatus for cleaning a surface of the solar cell panel. The control unit commands cleaning of the solar cell panel only when the power generation value decreases because of a contamination of the surface of the solar cell panel.

System for cleaning surface of solar cell panel

Provided is a low power consumption processor. The processor includes: a plurality of blocks; a memory storing instructions that control each of the plurality of blocks; and a multi power controller generates a signal that activates at least one of the plurality of blocks according to an address storing the instruction, and provides a normal power voltage or a reduction power voltage in response to the activation signal.

Low power consumption processor

Provided is a direct memory access (DMA) controller. The DMA controller includes a plurality of channel groups and a channel group controller. Each of the channel groups has a plurality of DMA channels, and the channel group controller controls enablement of the DMA channels in units of channel groups. Herein, the channel group controller enables the DMA channels of at least one of the channel groups in data transmission.

Direct memory access controller and data transmitting method of direct memory access channel

Provided is a bit stream processor using a reduced table lookup. The bit stream processor includes a bit stream exclusive register in a general purpose register in order to process data of a variable length effectively. Additionally, the bit stream processor an instruction of a table lookup method to which a prefix method is applied and a bit stream exclusive instruction in order to reduce an entire memory size.

Method of driving bit stream processor

Provided is a data processing circuit. A control unit outputs an operation control signal and a memory control signal. A plurality of program memories each outputs a command in response to the memory control signal. A plurality of arithmetic sections each selectively performs any one of the commands from the plurality of program memories in response to the operation control signal. Operation modes of the data processing circuit can be flexibly changed according to operation environments.

Arithmetic units responsive to common control signal to generate signals to selectors for selecting instructions from among respective program memories for SIMD / MIMD processing control

Disclosed is a V-BLAST system for a MIMO communication system. In the V-BLAST system for a MIMO communication system, a pseudo inverse matrix calculator receives a channel transfer function matrix including channel information and produces a cofactor matrix and a determinant for a pseudo inverse matrix. A norm & minimum calculator calculates a minimum index for the cofactor matrix outputted from the pseudo inverse matrix calculator, a weight vector selector selects a row vector having the minimum index and calculates a transposed matrix for the row vector; an adder adds the transposed matrix to a received input symbol, and a subtractor subtracts the determinant to the output. A demapper performs a determined function operation to the output and produces estimated information.

Processing device for a pseudo inverse matrix and V-BLAST system

Disclosed is a low power and high density source driver and a current driven active matrix organic electroluminescent device having the same, in which all elements operate at a normal voltage and all circuits of the source driver are shielded from a high voltage of a panel. The source driver includes: a shift register for generating an enable signal for storing data; a data latch circuit for storing digital data inputted from an exterior; a line latch circuit for sequentially storing the data in response to the enable signal and outputting the stored data in parallel at one time in response to a load signal; a current type digital-to-analog converter for converting the digital data outputted from the line latch circuit into an analog signal, the analog signal being outputted in a form of a current signal; and a high voltage shield circuit for transferring the output of the current digital-to-analog converter to source lines of an external panel and for shielding internal circuits from a high voltage of the panel. The shift register, the data latch circuit, the line latch circuit, the current type digital-to-analog converter and the high voltage shield circuit are driven at a normal voltage.

Low power and high density source driver and current driven active matrix organic electroluminescent device having the same

Provided is a data bus system for a micro controller which has an input/output (I/O) unit, a central processing unit (CPU), an internal memory unit, and a peripheral circuitry. The data bus system includes an external access bus used when data is output from the CPU or data is input to the I/O unit or the internal memory unit; an internal access bus used when data is input to the CPU, data is output from the I/O unit or the internal memory unit, or data is input to or output from the peripheral circuitry; and an internal memory test bus used when data is output from the internal memory unit and input to the I/O unit.

Data bus system for micro controller

A multiplying digital to analog converter comprising a digital to analog converter having a plurality of capacitors coupled in parallel, applying first signals to the capacitors during a sampling period, and applying second signals to the capacitors during an amplifying period, and an amplifier including a first amplifier electrically coupled to the digital to analog converter; a second amplifier electrically coupled to the first amplifier; and a first switch electrically coupled between an input end and an output end of the second amplifier, being turned off during a sampling period, and being turned off during an amplifying period.

Multiplying digital to analog converter and multipath pipe line analog to digital converter using the same

Growing community of inventors

Daejeon, South Korea

Jong-Dae Kim