Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

Jong Chen

Di-Son Kuo

Hung-Der Su

Chrong Jung Lin

Chrong-Jung Lin

Wen-Ting Chu

Chia-Ta Hsieh

Shui-Hung Chen

Yai-Fen Lin

Tze-Liang Lee

Hung-Cheng Sung

Hsin-Yu Chen

Jui-Chun Weng

Hsi-Cheng Hsu

Chih-Yu Wang

Shyh-Wei Cheng

Ji-Hong Chiang

Hung Der Su

Fan-Keng Yang

Chuan-Yi Ko

Chrong-Jong Lin

Wen Ting Chu

Chung-Hsien Hung

Shui Hung Chen

Chih-Hsien Chen

Yu-Mei Wu

Embodiments of mechanisms for forming a micro-electro mechanical system (MEMS) device are provided. The MEMS device includes a substrate and a MEMS substrate disposed on the substrate. The MEMS substrate includes a movable element, a fixed element and at least a spring connected to the movable element and the fixed element. The MEMS device also includes a polysilicon layer on the movable element.

Mechanism for forming MEMS device

Via layout with via groups placed in an interlocked arrangement for suppressing the crack propagation along the domain boundary between the via groups. A structure has a metal via pattern located in a dielectric layer and having a first via group and a second via group adjacent to each other. The first via group has at least two first line vias extending in a first direction, and the second via group has at least two second line vias extending in a second direction. The first via group and the second via group are placed in an interlocked arrangement, and a domain boundary along the first direction or the second direction between the first via group and said second via group is not straight.

Via layout with via groups placed in interlocked arrangement

A stacked-gate flash memory cell having a shallow trench isolation with a high-step of oxide and high lateral coupling is described. An unconventionally high isolation oxide layer is formed in a shallow trench isolation (STI) in a substrate. The deep opening in the space between the STIs is conformally lined with a polysilicon to form a floating gate extending above the opening. A conformal intergate oxide lines the entire floating gate. A layer of polysilicon overlays the intergate oxide and protrudes downward into the openings to form a control gate with increased coupling to the floating gate.

Stacked-gate flash memory cell with folding gate and increased coupling ratio

A new method of fabricating a stacked gate Flash EEPROM device having an improved stacked gate topology is described. Isolation regions are formed on and in a semiconductor substrate. A tunneling oxide layer is provided on the surface of the semiconductor substrate. A first polysilicon layer is deposited overlying the tunneling oxide layer. The first polysilicon layer is polished away until the top surface of the polysilicon is flat and parallel to the top surface of the semiconductor substrate. The first polysilicon layer is etched away to form the floating gate. The source and drain regions are formed within the semiconductor substrate. An interpoly dielectric layer is deposited overlying the first polysilicon layer. A second polysilicon layer is deposited overlying the interpoly dielectric layer. The second polysilicon layer and the interpoly dielectric layer are etched away to form a control gate overlying the floating gate. An insulating layer is deposited overlying the oxide layer and the control gate. Contact openings are formed through the insulating layer to the underlying control gate and to the underlying source and drain regions. The contact openings are filled with a conducting layer to complete the fabrication of the Flash EEPROM device.

Method to fabricate a flash memory cell with a planar stacked gate

The invention is an easy-to-assemble LED display driven by a simple circuit for any graphics and text by utilizing a plurality of LED display elements with built-in resistors directly installed on a display with power to light up the LED elements and display texts or graphics. This invention, in particular, allows the user compose different texts or graphics by arranging at will the positions of the LED display elements with built-in resistors on a specific circuit.

Easy-to-assembly LED display for any graphics and text

A vertical memory device on a silicon semiconductor substrate is formed by the following steps. Form an array of isolation silicon oxide structures on the surface of the silicon semiconductor substrate. Form a floating gate trench in the silicon semiconductor substrate between the silicon oxide structures in the array, the trench having trench sidewall surfaces. Dope the sidewalls of the floating gate trench with a threshold implant through the trench sidewall surfaces. Form a tunnel oxide layer on the trench sidewall surfaces, the tunnel oxide layer having an outer surface. Form a floating gate electrode in the trench on the outer surface of the tunnel oxide layer. Form source/drain regions in the substrate self-aligned with the floating gate electrode. Form an interelectrode dielectric layer over the top surface of the floating gate electrode. Form a control gate electrode over the interelectrode dielectric layer over the top surface of the floating gate electrode. Form a source line by the step of performing a self-aligned etch followed by a source line implant.

Flash memory cell with vertically oriented channel

A new process is provided whereby LDD regions for HV CMOS devices and for LV CMOS devices are created using one processing sequence. The gate electrodes for both the High Voltage and the Low Voltage devices are created on the surface of a silicon substrate. The High Voltage LDD (HVLDD) is performed self-aligned with the HV CMOS gate electrode, a gate anneal is performed for both the HV and the LV CMOS devices. The Low Voltage LDD (LVLDD) is performed self-aligned with the LV CMOS gate electrodes. The gate electrodes of the CMOS devices are after this completed with the formation of the gate spacers, the source/drain implants and the back-end processing that is required for CMOS devices.

Integration process to increase high voltage breakdown performance

A method for forming a passivation layer on at least one copper conductive element in a semiconductor structure and the devices formed are described. In the method, after a top surface of a semiconductor device that contains copper conductors embedded in an insulating layer is first planarized by a chemical mechanical polishing method, an etching process is conducted to create a stepped or corrugated surface between the surface of the copper conductor and the surface of the insulating layer, so that when a passivation layer is later deposited on top of the semiconductor structure, the same stepped or corrugated surface is reproduced in the passivation layer and thus providing a mechanical interlock between the passivation layer and the copper conductor for preventing adhesion failure or peeling of the passivation layer from the surface of the semiconductor structure.

Method for forming a passivation layer on copper conductive elements

A method is disclosed for forming LDDs (Lightly Doped Drains) in high voltage devices employed in non-volatile memories and DDDs (Doubly Doped Drains) in flash memory applications. The high voltage device is formed by using two successive ion implantations at a tilted angle which provides an improved gradation of doped profile near the junction and the attendant improvement in junction breakdown at higher voltages. The doubly doped drain in a stacked flash memory cell is also formed by two implantations, but at an optimum tilt-angle, where the first implantation is lightly doped, and the second, heavily doped. The resulting DDD provides faster program speed, reduced program current, increase read current and reduced drain disturb in the flash memory cell.

Tilt-angle ion implant to improve junction breakdown in flash memory application

A flash memory cell and the making thereof is disclosed where the cell has a damascene-like stacked gate. The stacked gate is formed not by blanket depositing a first polysilicon layer and then subtractively etching to form a floating gate followed by the depositing of a second polysilicon layer separated by an intervening inter-gate dielectric layer over the floating gate. On the contrary, a trench is formed in a nitride layer formed over a substrate using a modified damascene process. The first polysilicon layer is conformally deposited into the damascene-like trench to form the floating gate of the disclosed cell. Then, a layer of inter-gate dielectric layer is formed over the first polysilicon layer in the trench, followed by the forming of a second polysilicon layer over the dielectric layer, thus forming the damascene-like stacked gate of this invention. The disclosed method alleviates the problem of having poly residues resulting from defects caused by etching the conventionally deposited polysilicon layer. Furthermore, etching over active region can also cause damage to the underlying substrate, which is not the case here. In addition, the method enables the incorporation of the curved structure of the floating gate of this invention into the area that increases the coupling ratio of the flash memory cell.

Flash memory structure with stacking gate formed using damascene-like structure

A layer of well oxide is grown over the n-well or p-well region of the semiconductor substrate. A deep n-well implant is performed in high voltage device region, followed by a deep n-well drive-in of the deep n-well implant. The well oxide is removed; the field oxide (FOX) region is created in the high voltage device region. A layer of sacrificial oxide is deposited on the surface of the semiconductor substrate. A low voltage cluster n-well implant is performed in the high voltage PMOS region of the semiconductor substrate followed, for the high voltage NMOS region, by a low voltage cluster p-well implant which is followed by a buried p-well cluster implant.

Implant method to improve characteristics of high voltage isolation and high voltage breakdown

A method of manufacture of self-aligned floating gate, flash memory device on a semiconductor substrate includes the following steps. Form a blanket silicon oxide layer over the substrate. Form a blanket floating gate conductor layer over the silicon oxide layer. Pattern the blanket silicon oxide layer, the floating gate conductor layer and the substrate in a patterning process with a single floating gate electrode mask forming floating gate electrodes from the floating gate conductor layer and the silicon oxide layer; and simultaneously form trenches in the substrate adjacent to the floating gate electrode and aligned with the floating gate electrodes thereby patterning the active region in the substrate. Form a blanket dielectric layer on the device filling the trenches and planarized with the top surface of the floating gate electrodes. Form an interconductor dielectric layer over the device including the floating gate electrodes. Form a control gate conductor over the interconductor dielectric layer.

Method of manufacture of self-aligned floating gate, flash memory cell and device manufactured thereby

A method is provided for forming a stacked-gate flash memory cell having a shallow trench isolation with a high-step of oxide and high lateral coupling. This is accomplished by first depositing an unconventionally high or thick layer of nitride and then forming a shallow trench isolation (STI) through the nitride layer into the substrate, filling the STI with isolation oxide, removing the nitride thus leaving behind a deep opening about the filled STI, filling conformally the opening with a first polysilicon layer to form a floating gate, forming interpoly oxide layer over the floating gate, and then forming a second polysilicon layer to form the control gate and finally forming the self-aligned source of the stacked-gate flash memory cell of the invention. A stacked-gate flash memory cell is also provided having a shallow trench isolation with a high-step of oxide and high lateral coupling.

Method to increase the coupling ratio of word line to floating gate by

A process for integrating the fabrication of a flash memory cell, on a first region of a semiconductor substrate, with the fabrication of salicided peripheral devices, on a second region of the semiconductor substrate, has been developed. The flash memory cell features SAC contact structures, located between stacked gate structures, contacting underlying source/drain regions. The stack gate structures are comprised of a polycide control gate shape, on a dielectric layer, overlying a polysilicon floating gate shape. The performance of the peripheral devices are increased via use of metal silicide layers, located on the top surface of a polysilicon gate structure, as well as on the adjacent heavily doped source/drain regions.

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Taipei, Taiwan

Jong Chen