Skhynix Inc.

Samsung Electronics Co., Ltd.

Jong-Bum Park

Kee-Jeung Lee

Jae-Min Lee

Jeong-Yeop Lee

Sang-Do Lee

Jun-Soo Jang

Dong-Su Park

Seung-hoon Lee

Sang-Young Lee

Jin-Man Kim

Kyoung-ho Moon

Hee-Sam Kim

Kwang-Bo Sim

Hee-seuk Yang

Jea-Eun Jess Shim

A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.

Semiconductor device and method for fabricating the same

An ESC may include a dielectric layer, an electrode, a pedestal, a heater, an adhesive and a protecting ring. The dielectric layer may be configured to support a substrate. The electrode may be disposed in the dielectric layer and is configured to form plasma over the substrate. The pedestal may be disposed under the dielectric layer. The heater may be disposed between the pedestal and the dielectric layer and is configured to heat the substrate. The adhesive may be disposed between the pedestal and the heater, and between the heater and the dielectric layer. The protecting ring may be configured to surround the adhesive. The protecting ring may include a plasma-resistant material.

Electrostatic chuck and apparatus for processing a substrate including the same

Provided is an on-chip reference current generating circuit for generating a reference voltage that can be digitally calibrated and is substantially not affected by changes in temperature and/or supply voltage. The on-chip reference current generating circuit includes a summing circuit for receiving a first current having a negative temperature coefficient and a second current having a positive temperature coefficient, and outputting a third current based upon, is a sum of, the first and second currents; and a digital calibration circuit for calibrating the third current to be the reference current in response to a digital control signal. Using the on-chip reference current generating circuit, it is possible to precisely and digitally calibrate an offset between currents due to a change in temperature and/or supply voltage.

On-chip reference current and voltage generating circuits

Growing community of inventors

Seoul, South Korea

Jong-Bum Park