Samsung Electronics Co., Ltd.

Jong-bok Tcho

Jeong-ho Bang

Woo-seop Jeong

Hyun-seop Shim

Sung-ryul Kim

Gil-Young Koh

Ja-hyun Koo

A memory device, such as a DDR SDRAM, may be provided in which subsets of data output circuits of the device can be selectively enabled to allow sets of data output pins to be connected in common in a testing configuration. In some embodiments, a memory device includes a plurality of data output circuits, respective ones of which are configured to receive data from respective internal data lines and respective ones of which are coupled to respective data input/output pins. The device further includes a data output control circuit operative to selectively enable subsets of the plurality of data output circuits to drive their respective corresponding data input/output pins responsive to an externally-applied control signal. The data output control circuit may be operative to selectively cause subsets of the plurality of data output circuits to present a high impedance at their respective corresponding data input/output pins. The invention may be embodied as devices and methods.

Memory devices with selectively enabled output circuits for test mode and method of testing the same

A method of electrically testing a semiconductor device preferably includes connecting a common input/output signal channel (line) of a socket board to two or more data pins of the semiconductor device. Signals output from the semiconductor device may be sequentially read via the short-circuited input/output signal lines of the socket board by carrying out a byte operation function. The throughput of a semiconductor test system can thereby be increased by increasing the number of devices that can be tested in parallel.

Method of electrically testing semiconductor devices

When high speed memory devices are tested using a tester having a lower operating frequency than the operational speed of the memory device, limit conditions for the tester signals are required to prevent the interference between the tester and device signals. The present invention provides the limit conditions for the shift and strobe signal. The strobe signal is delivered to comparators with a delivery delay time defining the dead time zone. The shift signal controls the data path of the device to and from a driver and a comparator. When the strobe signal is within the present test cycle, the shift signal of a read cycle must be activated at the same time or earlier than the activation time of the WE/ signal of the next write cycle and the shift signal of a write cycle must start at the same time or earlier than the activation time of the OE/ signal of the next read cycle. When the strobe signal is outside of the test cycle, the shift signal must meet prescribed maximum and minimum timing conditions.

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Kyungki-do, South Korea

Jong-bok Tcho