Samsung Electronics Co., Ltd.

Jong-bo Shim

Ji-hwang Kim

Cha-Jea Jo

Sang-Uk Han

Won-Il Lee

Jang-woo Lee

Un-Byoung Kang

Young-kun Jee

Young-Min Kim

Yong-hwan Kwon

Tae-Je Cho

Yun-seok Choi

Jung-Woo Kim

Kyoung-sei Choi

Min-Ok Na

Kyung-suk Oh

Yung-cheol Kong

Hyo-Chang Ryu

Moon-Gi Cho

Gun-Ho Chang

Ji-sun Hong

Gun-ho Chang

Jang-Woo Lee

Jong-Yun Myung

Woo-hyun Park

Hyo-Eun Kim

Jae-myeong Cha

Sang-uk Han

A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a plurality of first chip connection units to connect the first package substrate to the first semiconductor chip, an interposer on the first semiconductor chip, the interposer having a width greater than a width of the first semiconductor chip in a direction parallel to an upper surface of the first package substrate, and an upper filling layer including a center portion and an outer portion, the center portion being between the first semiconductor chip and the interposer, and the outer portion surrounding the center portion and having a thickness greater than a thickness of the center portion in a direction perpendicular to the upper surface of the first package substrate.

Semiconductor package

An image sensor package includes an image sensor chip on a package substrate, a logic chip on the package substrate and perpendicularly overlapping the image sensor chip, and a memory chip on the package substrate and perpendicularly overlapping the image sensor chip and logic chip. The logic chip processes a pixel signal output from the image sensor chip. The memory chip is electrically connected to the image sensor chip through a conductive wire and stores at least one of the pixel signal from the image sensor chip or a pixel signal processed by the logic chip. The memory chip receives the pixel signal output from the image sensor chip through the conductive wire and receives the pixel signal processed by the logic chip through the image sensor chip and the conductive wire.

Image sensor package

A semiconductor package includes a first semiconductor chip, a second semiconductor chip attached to an upper surface of the first semiconductor chip, a silicon heat-dissipation body thermally connected to at least one of the first semiconductor chip and the second semiconductor chip, and a molding member configured to surround the first semiconductor chip and the second semiconductor chip and exposing an upper surface of the silicon heat-dissipation body.

Semiconductor package and method of manufacturing the same

A substrate structure for an image sensor module includes a module substrate including a sensor mounting hole, a reinforcing plate on a lower surface of the module substrate, an image sensor chip on the reinforcing plate within the sensor mounting hole, and a reinforcing pattern in the module substrate. The reinforcing plate covers the sensor mounting hole. An upper surface of the image sensor chip may be exposed by the module substrate. The reinforcing pattern is adjacent to the sensor mounting hole and extends in at least one direction.

Substrate structures for image sensor modules and image sensor modules including the same

A semiconductor package includes a substrate, a rewiring layer, a plurality of semiconductor chip stack structures, and a second semiconductor chip. The rewiring layer is disposed on an upper surface of the substrate. The rewiring layer includes a concave portion. The semiconductor chip stack structures include a plurality of first semiconductor chips. The first semiconductor chips are disposed on the rewiring layer. The first semiconductor chips are spaced apart from each other in a horizontal direction. The second semiconductor chip is disposed within the concave portion. The second semiconductor chip is configured to electrically connect each of the plurality of semiconductor chip stack structures to each other.

Semiconductor package including a rewiring layer with an embedded chip

A printed circuit board (PCB) includes a substrate base including at least two chip attach regions spaced apart from one another, a plurality of upper pads disposed in the at least two chip attach regions of the substrate base, an accommodation cavity overlapping a part of each of the at least two chip attach regions and recessed in an upper surface of the substrate base, and at least one spacing groove recessed in the upper surface of the substrate base. The at least one spacing groove is connected to the accommodation cavity, and extends in a region between the at least two chip attach regions.

Printed circuit board and semiconductor package including the same

A method of manufacturing a semiconductor package includes forming at least two partial package chip stacks, each partial package chip stack including at least two semiconductor chips each including a plurality of through substrate vias (TSVs), and including a first mold layer surrounding side surfaces of the at least two semiconductor chips, and sequentially mounting the at least two partial package chip stacks on a package substrate in a direction vertical to a top surface of the package substrate, such that the at least two partial package chip stacks include a first partial package chip stack and a second partial package chip stack directly connected to the first partial package chip stack.

A semiconductor package includes a package member and a stress controlling layer. The package member includes an encapsulation layer and at least one chip. The encapsulation layer encapsulates the at least one chip. The stress controlling layer is disposed on a surface of the package member. The stress controlling layer has an internal stress to the extent that the stress controlling layer prevents the package member from having warpage.

Semiconductor package and manufacturing method thereof

A stack type semiconductor package includes: a lower semiconductor package including a lower package substrate, and a lower semiconductor chip which is mounted on the lower package substrate and includes a first surface facing a top surface of the lower package substrate and a second surface opposite to the first surface; an upper semiconductor package including an upper package substrate and an upper semiconductor chip which is mounted on the upper package substrate; an inter-package connection unit which connects the lower package substrate and the upper package substrate; a heat dissipation member which is formed on the second surface of the lower semiconductor chip; and an interconnection unit which is formed on a bottom surface of the upper package substrate, and is adhered to the heat dissipation member to connect the lower semiconductor chip and the upper package substrate.

Stack type semiconductor package

A bump structure includes a first bump and a second bump. The first bump is disposed on a connection pad of a substrate. The first bump includes a lower portion having a first width, a middle portion having a second width smaller than the first width, and an upper portion having a third width greater than the second width. The second bump is disposed on the upper portion of the first bump.

Bump structure, having concave lateral sides, semiconductor package having the bump structure, and method of forming the bump structure

A package-on-package assembly includes first and second packages and an adhesion member positioned between the first and second packages and adhering the first and second packages to one another. The first package may include a first substrate having a first surface and a second surface facing each other and including a land pad formed on the first surface, a first semiconductor chip formed on the first surface, and a first encapsulant member encapsulating the first surface and the first semiconductor chip and including a through-via spaced apart from the first semiconductor chip and exposing the land pad and a trench formed between the first semiconductor chip and the through-via, and wherein at least a portion of the trench is filled with adhesion member material.

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Asan-si, South Korea

Jong-bo Shim