Nvidia Corporation

Jonathon Stuart Ramsay Evans

Jerome Francis Duluk, Jr

Lacky V Shah

Samuel Hammond Duncan

Steven E Molnar

Sean Jeffrey Treichler

James Leroy Deming

Wishwesh Anil Gandhi

Mark Hairgrove

Philip Browning Johnson

Daniel Elliot Wexler

Vyas Venkataraman

Jeffrey M Smith

Hemayet Hossain

Geoffrey Gerfin

Vikram Sethi

Terje Bergstrom

Piyush Patel

Various embodiments include techniques for accessing extended memory in a parallel processing system via a high-bandwidth path to extended memory residing on a central processing unit. The disclosed extended memory system extends the directly addressable high-bandwidth memory local to a parallel processing system and avoids the performance penalties associated with low-bandwidth system memory. As a result, execution threads that are highly parallelizable and access a large memory space execute with increased performance on a parallel processing system relative to prior approaches.

High bandwidth extended memory in a parallel processing system

One embodiment of the present invention includes techniques to support demand paging across a processing unit. Before a host unit transmits a command to an engine that does not tolerate page faults, the host unit ensures that the virtual memory addresses associated with the command are appropriately mapped to physical memory addresses. In particular, if the virtual memory addresses are not appropriately mapped, then the processing unit performs actions to map the virtual memory address to appropriate locations in physical memory. Further, the processing unit ensures that the access permissions required for successful execution of the command are established. Because the virtual memory address mappings associated with the command are valid when the engine receives the command, the engine does not encounter page faults upon executing the command. Consequently, in contrast to prior-art techniques, the engine supports demand paging regardless of whether the engine is involved in remedying page faults.

Techniques for supporting for demand paging

A time slice group (TSG) is a grouping of different streams of work (referred to herein as 'channels') that share the same context information. The set of channels belonging to a TSG are processed in a pre-determined order. However, when a channel stalls while processing, the next channel with independent work can be switched to fully load the parallel processing unit. Importantly, because each channel in the TSG shares the same context information, a context switch operation is not needed when the processing of a particular channel in the TSG stops and the processing of a next channel in the TSG begins. Therefore, multiple independent streams of work are allowed to run concurrently within a single context increasing utilization of parallel processing units.

Concurrent execution of independent streams in multi-channel time slice groups

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Santa Clara, CA, United States of America

Jonathon Stuart Ramsay Evans