Motorola Corporation

Jonathon G Greenwood

Douglas W Hendricks

Frank J Juskey

Ovidiu Neiconi

Robert Kenneth Doot

Reed A George

Thomas P Kirby

James George Lance, Jr

Edward Juchniewicz

A novel process for plating a substrate without solder mask wherein the substrate is coated with a polymer catalyst to assist adhesion of conductive metal to the substrate. Next, a first plating mask photopolymer, or plating resist, is coated over the polymer catalyst, a circuit pattern is imaged onto the first plating mask and the first plating mask is developed to reveal windows, or circuit traces, in the first plating mask corresponding to the circuit pattern to be embodied on the substrate. Thereafter, a first conductive material such as copper is plated into the windows, and, thereafter, a second conductive material such as nickel may be plated into the windows on top of the first conductive material. Then, the first plating mask is removed from the substrate, leaving behind the conductive material in the form of the desired circuit pattern. Next, a second plating mask photopolymer is formed over the substrate and conductive materials, and an I/O interconnect mask corresponding to the I/O interconnect pads is photo-optically imaged onto the second plating mask and the second plating mask is developed to remove portions thereof, creating 'interconnect voids,' corresponding to the interconnect pads. Thereafter, a third conductive material such as gold is plated into the interconnect voids to create conductive I/O pads.

Method for plating a substrate to eliminate the use of a solder mask

A method of producing multi-layered chip carriers by coating the surface of a base layer with a photosensitive dielectric material which forms a dielectric layer; curing at least a portion of the dielectric layer by exposure to radiation; depositing a catalyst on the cured portion of the dielectric layer to form a sensitized dielectric layer; applying a photoresist layer upon the sensitized dielectric layer; curing at least a portion of the photoresist layer; developing the cured photoresist layer by removing uncured portions, thereby exposing corresponding portions of the underlying sensitized dielectric layer; forming conductors on the exposed dielectric layer; stripping the cured photoresist layer: coating a layer of photosensitive dielectric material upon the cured dielectric layer; and repeating the steps to produce successive layers which form a multi-layer chip carrier having a plurality of conductor layers separated by layers of insulating dielectric material.

Method for producing high density multi-layer integrated circuit carriers

A method and apparatus improves a distribution of an underfill material (504) applied between a flip chip die (202) and a circuit board (310) at a flip chip site (302) having a solder mask (308). An aperture (304) is formed (806) in the solder mask (308) by removing a predetermined majority of the solder mask (308) from the circuit board (310) within the flip chip site (302) before mounting the flip chip die (202). Then the flip chip die (202) is mounted (810) to the flip chip site (302). The underfill material (504) is then applied (812, 814, 816) such that the underfill material (504) flows into the aperture (304), thus improving the distribution of the underfill material (504).

Method for improving distribution of underfill between a flip chip die

An integrated circuit chip carrier (100) provides an improved mounting pad density. The chip carrier (100) includes a flexible substrate (102) with pads (104) on the top surface for interconnection with an attached integrated circuit chip (302). The chip carrier (100) further includes a mounting pad array (502) on the bottom surface having an interconnection with the pads (104), and a rigid substrate (202) having an array of holes (204) extending through it. The top surface of the rigid substrate (202) is fixedly attached to the bottom surface of the flexible substrate (102). Individual holes of the array of holes (204) correspond to and align with individual pads of the mounting pad array (502). The chip carrier (100) further includes solder (206) disposed on the mounting pad array (502) and extending through the array of holes (204) beyond the bottom surface of the rigid substrate (202) for mounting the integrated circuit chip carrier (100) to a circuit bearing substrate (700).

Method and apparatus for an integrated circuit chip carrier having

A method of interconnecting circuit modules (30) to mother boards (50) each having a plurality of mating solder pads (32, 52) is available. The solder pads (32, 52) have respective pairs of arms (40, 42) and (54, 56) with a venting channel (36, 58) formed between each pair of arms to vent solder medium when the solder pads are reflowed to interconnect the circuit modules and mother boards.

Method and structure for attaching a circuit module to a circuit board

A wire bond pad arrangement (104) has an improved pad density for providing a plurality of wire bond terminations for interconnection with corresponding terminations (604) of an IC chip (302. The wire bond pad arrangement (104) includes a substrate (102) and a plurality of pads (912) disposed on the substrate (102) adjacent to one another to form a row of pads (912). Each of the pads (912) is formed in a trapezoidal shape having short and long sides parallel to one another and substantially perpendicular to a line from a central point of the pad (912) to a central point of the corresponding termination (604) of the IC chip (302). The long sides of adjacent pads (912) are positioned alternately towards and away from the corresponding terminations (604) of the IC chip 302).

Wire bond pad arrangement having improved pad density

A station (10) in a manufacturing line (12) for the accurate placement of solder balls (30) on a ball grid array package and for the removal of excess solder balls comprises a substrate (4) having an array of solder pads (7), and an adhesion layer (8) on the solder pads. The station further comprises a stencil (16) placed on top of the substrate and having a height between 1/4 times the diameter of one of the solder balls and 5/4 times the diameter of one of the balls, the stencil having an array of apertures (18) corresponding to the array of solder pads and substantially exposing each of the solder pads of the array, a pallet (2) for holding and transporting the substrate to the stencil and further along the manufacturing line, a dispenser (26) for pouring solder balls in bulk over the stencil, a vibration device (20) coupled to the station for urging the solder balls into the apertures of the stencil and onto the adhesion layer above the solder pads, and a moving directed column of air (24) across the surface of the stencil to remove excess solder balls from the stencil.

Growing community of inventors

Boynton Beach, FL, United States of America

Jonathon G Greenwood