Cypress Semiconductor Corporation

Jonathon C Stiff

Nathan Y Moyal

Aaron Brennan

Jay A Kuhn

King Hong Kwan

Mike McMenamy

Michael McMenamy

Adam El-Mansouri

Mandonev Rajasekaran

A differential-to-single ended converter circuit can include a latching circuit having first and second latch field effect transistors (FETs) with drains and gates cross-coupled between a first latch node and a second latch node. The source-drain paths of the first and second latch FETs are coupled to a first reference potential node via separate current paths. A sense circuit can include a first sense FET having a source-drain path coupled between the first sense node and the first reference potential node, and a gate coupled to a first input node. A second sense FET has a source-drain path coupled between the second sense node and the first reference potential node, and a gate coupled to a second input node. An output circuit can have a first output FET with a source-drain path coupled between a first output supply node and an output signal node, and a gate coupled to the first latch node, and a second output FET with a source-drain path coupled between the output signal node and a second output supply node.

Differential-to-single ended signal converter circuit and method

Disclosed is an oscillator circuit, comprising a crystal oscillator, an amplifier having an input and an output coupled across the crystal oscillator, a comparator having a reference input and an input coupled to the crystal oscillator and a pole network coupled between the comparator and the amplifier.

Amplitude regulated resonant oscillator with sampled feedback

Circuits and methods for aligning two or more signals including a first and second signal. In one embodiment, a shift register generates two or more shifted copies of the second signal, and each of a plurality of phase detectors receives the first signal and one of the shifted copies of the second signal, each phase detector providing an output indicating whether the first signal is substantially aligned with the shifted copy of the second signal. A multiplexer may also be provided for receiving each of the shifted copies of the second signal, the multiplexer having a plurality of select lines coupled with the output signals of the phase detectors. Some embodiments may include a power saving mode.

Method and circuit for rapid alignment of signals

A delay limit detect circuit can determine the delay of a current steering delay cell, like those utilized in a voltage controlled oscillator (VCO), by monitoring a current (I) that tracks a delay cell current (I). When the monitored current (I) outside of a limit, a signal LIMIT can be activated. A monitored current (I) can be generated by a control replica circuit having the same circuit component types as a control circuit within a delay cell. Such limit detection can provide a way to prevent a ring VCO from entering a runaway state, particularly in cases where a maximum frequency can be reached before a maximum control voltage is reached.

Delay circuit limit detection circuit and method

A circuit for generating a reference current, comprising a positive feedback loop, a negative feedback loop, and a floating current mirror coupled to the positive feedback loop. The negative feedback loop may operate to divert current directly from the floating mirror, and may also operate to divert current from the floating mirror by using a voltage follower. The circuit may operate with a minimum supply voltage of approximately the sum of the threshold voltage of a transistor plus three drain saturation voltages, in one example.

Circuit and method for implementing a low supply voltage current reference

A phase locked loop (PLL) can include a test loop filter () that generates a control voltage (V) for input to a voltage controlled oscillator (VCO). In a test mode, a control voltage can be varied and resulting output frequencies recorded, from which an open loop bandwidth can be determined. A control voltage can be varied by enabling a switch element (-) that can provide a current path through load resistance (RL) of test loop filter (). Current provided to the test loop filter can be varied according to test signals to provide a variable control voltage (V).

Open loop bandwidth test architecture and method for phase locked loop (PLL)

An amplifier circuit operable to provide symmetric current limiting. The amplifier circuit includes a common source amplifier for sourcing a current and receiving an voltage input, a current source, and a current limiting device coupled between the common source amplifier and the current source. The current limiting device is operable to limit the current sourced by the common source amplifier. A bias network coupled to the current limiting device biases the current limiting device. An output is coupled to the current limiting device. The amount of current that is sourced to the output of the amplifier circuit may be limited, such that current limiting is symmetrical.

Oscillator amplifier circuit operable to provide symmetric current limiting and method of same

A method and an apparatus to reduce duty cycle distortion are described. The apparatus may include a first current-mode logic (CML) circuit block comprising a positive input and a negative input and a second CML circuit block coupled in series to the first CML circuit block. The second CML circuit block may comprise a positive output, a negative output and a first transistor coupled between the positive input and the positive output. The second transistor may be coupled between the negative input and the negative output of the second CML circuit block.

Method and an apparatus to reduce duty cycle distortion

An oscillator circuit is provided that is preferably a crystal oscillator, where voltage placed across the crystal is regulated. The regulated voltage or amplitude of the cyclical signal across the crystal is monitored and maintained through a regulation circuit that measures a peak voltage across the crystal. Once the peak voltage exceeds a predetermined setpoint value, then a controller within the regulation circuit will reduce a biasing current through an amplifying transistor within the amplifier coupled across the crystal input and output nodes. By regulating the biasing current, gain from the amplifier is also regulated so that unwanted non-linearities and harmonic distortion is not induced within the crystal to cause frequency distortion and unwanted modes of oscillation within the crystal. The amplifier is preferably symmetrical in that the amplifier sources and sinks equal current to reduce unwanted peaks at the negative or positive half cycles of the sinusoidal signal.

Regulated, symmetrical crystal oscillator circuit and method

A voltage-to-current converter circuit is disclosed. In one embodiment, the present invention includes a first metal oxide semiconductor field effect transistor (MOSFET) stage operable in a low to medium power range. The present invention also includes a second MOSFET stage operable in a medium to high power range. An additive circuit is utilized to add the contributions of both the first MOSFET stage and the second MOSFET stage. A subtractive circuit is further used to subtract either the first MOSFET stage or the second MOSFET stage when both the first MOSFET stage and the second MOSFET stage are operating in the medium power range and outputting current in a voltage-to-current converting circuit.

Rail-to-rail input linear voltage to current converter

A current controlled delay circuit is disclosed. Two currents of constant sum are generated to control the delay of the circuit. The circuit includes a differential pair to switch one of the two currents from one leg of the circuit to another leg of the circuit. The circuit includes a cross-coupled pair to switch the other of the two currents from one leg of the circuit to another leg of the circuit. The circuit may include a fixed or variable load.

Current controlled delay circuit

An apparatus comprising a pump up circuit, a pump down circuit and an output circuit. The pump up circuit may be configured to generate a pump up signal and receive a first source bias. The pump down circuit may be configured to generate a pump down signal and receive a second source bias. The output circuit may be configured to receive the pump up and pump down signals and generate an output signal. The pump up circuit may be configured to precharge the first source bias and the pump down circuit may be configured to precharge the second source bias signal.

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Mountlake Terrace, WA, United States of America

Jonathon C Stiff