Apple Inc.

Jonathan Ying Fai Tong

Brett Stanley Feero

David Edward Kroesche

Christopher Colletti

Matthew C Stone

So Min Song

Gagan Anand

A processor with reduced interrupt latency is disclosed. An apparatus includes a processor core and a cache subsystem having a cache controller and a cache. The processor core is configured to submit, to the cache controller, requests for access to the cache, wherein a given request for access to the cache specifies whether the given request is abandonable or non-abandonable in an event of an interrupt request. In response to a particular interrupt request, the processor core may provide an indication to cause the cache controller to abandon requests for access to the cache identified as abandonable. After receiving an acknowledgement from the cache controller that the abandonable requests have been abandoned, the processor core may begin execution of an interrupt handler in order to service the interrupt request.

Growing community of inventors

Austin, TX, United States of America

Jonathan Ying Fai Tong