Texas Instruments Corporation

Jonathan William Nafziger

Veeramanikandan Raju

Ariton E Xhafa

Minghua Fu

Jyothsna Kunduru

Mathew Giaramita

Arvind Kandhalu

A system is provided. In some examples, the system includes a control circuit and a plurality of monitor circuits including a first monitor circuit. In a production mode, the control circuit is configured to test the plurality of monitor circuits. In a storage mode after testing the plurality of monitor circuits in the production mode, the control circuit is configured to test the plurality of monitor circuits more than once. In an assembly mode after testing the plurality of monitor circuits in the storage mode, the control circuit is configured to test the plurality of monitor circuits. In one or more examples, the control circuit is configured to skip the storage mode and test the plurality of monitor circuits in the assembly mode after testing in the production mode.

Operating modes for testing monitor circuits

Methods, apparatus, systems, and articles of manufacture are disclosed to improve one-hop extension in wireless battery management systems. An example apparatus is to cause transmission of an instruction to a first battery monitoring node (BMN) of a vehicle, the first BMN in communication with the apparatus, the instruction to cause the first BMN to operate as a repeater for a second BMN of the vehicle, the second BMN noncommunicative with the apparatus. The example apparatus is to process an acknowledgement from the first BMN indicating that the first BMN has configured to operate as the repeater. Additionally, the example apparatus is to cause transmission of a communication to at least the first BMN indicating a time at which at least the first BMN is to perform a first action associated with a first battery and the second BMN is to perform a second action associated with a second battery.

Methods, apparatus, and articles of manufacture to improve one-hop extension in wireless battery management systems

An apparatus includes a memory device and a microcontroller device integrated with the memory device. The microcontroller device is adapted to be communicatively coupled to a processor device and is configured to manage access by the processor device to data stored on the memory device. Managing access by the processor device to the data stored on the memory device includes setting an access permission for controlled data stored by the memory device based on authorization data stored in the memory device. Managing access by the processor device further includes receiving, from the processor device, a request to access the controlled data. Managing access by the processor device further includes determining whether to initiate access to the controlled data by the processor device based on the access permission.

System and method for providing limited utilization run time application control as a service in microcontrollers

A system including a bus, a processor coupled to the bus, a non-volatile memory coupled to the bus, circuitry for providing a detected condition, and a secure controller. The secure controller is coupled to the circuitry for providing a detected condition and to selectively enable communication of information between the non-volatile memory and the bus in response to the detected condition.

Processor and memory system to selectively enable communication

An integrated circuit and method of performing a reliability screen of an electrically programmable non-volatile memory array in the integrated circuit. At a first memory address of the array, a most stringent value of a sensing reference level at which correct data are read is identified. The remainder of the addresses of the array are evaluated in sequence, beginning at the value determined for the first address, and incrementally adjusting the sensing reference level for each, if necessary, until correct data are read at that address. The sensing reference level may be a reference current applied to a sense amplifier, against which read current from the addressed memory cell is compared, or may be control gate voltage applied to the control gate of a floating-gate transistor in the addressed memory cell. The process continues until all addresses in the memory array have been evaluated, following which the reference level identifies the strength of the weakest cell in the array, and the weakest address can be identified.

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Houston, TX, United States of America

Jonathan William Nafziger