University of Florida Research Foundation, Incorporated

Brookhaven Science Associates, Lcc

Jonathan William Cruz

Swarup Bhunia

Prabuddha Chakraborty

Tamzidul Hoque

Pravin Dasharth Gaikwad

Prabhat Kumar Mishra

Naren Masna

Abhishek Anil Nair

Toan Trung Nguyen

Sudipta Paria

Junjun Huan

Various embodiments of the present disclosure provide electromagnetic based secure contact-less integrity verification for an integrated circuit. In one example, an embodiment provides for mapping a signal to a pseudo-random number generator (PRNG) seed value, generating a PRNG output digital signal based on the PRNG seed value, encrypting the PRNG output digital signal based on a cipher function and a key, and generating an electromagnetic signal associated with the PRNG output digital signal to facilitate non-contact sensing of the electromagnetic signal by a probing system.

Electromagnetic based secure contact-less integrity verification of hardware and/or software for integrated circuits

A joint compression and encryption system is configured to retrieve, from a local memory or image capture device, an image file including a first plurality of segments. The system is further configured to identify, for one or more segment of the first plurality of segments, a matching segment in a local segmentation repository. The system is further configured to compress remaining segments of the first plurality of segments for which no matching segment was identified into a compressed remaining segment set. The system is further configured to transmit, via an unsecure communication channel and to a second computing entity, the identifications of the matching segments, and the compressed remaining segment set. The system is further configured to, prior to retrieving the image file, perform a handshake or calibration process. The system is further configured to encrypt the matching segments using a key into an encrypted segment set and transmit the key to the second computing entity. In embodiments, the second computing entity, using the key, decrypts the encrypted segment set.

Predictive joint compression and encryption for images and videos

Various embodiments of the present disclosure provide a scan-based architecture for register-transfer-level (RTL) or gate-level designs that improves the security of scan chain-based design-for-testability (DFT) structures. In various embodiments, the scan-based architecture includes invisible scan chains that are hidden in such a way that an attacker cannot easily identify or locate the invisible scan chains for exploitation and revealing internal secure information of the design. The invisible scan chains are dynamically configurable into a scan chain with select flip-flops, such that scan paths of the invisible scan chains may be different between different designs, chips, or testing operations. Various embodiments further employ key-based obfuscation by combining a scan control finite state machine with existing state machines within a design, which improves design security against unauthorized use and increases confidentiality. Specific sequences of key patterns cause the design to transition into a test mode or a normal mode.

Invisible scan architecture for secure testing of digital designs

Embodiments of the present disclosure provide methods, apparatus, and computer program products for generating an insertion netlist for a target circuit configured for inserting a malicious design alteration into the circuit based on a design identifying reference trigger nets. Features are extracted for each net identified in a netlist for the circuit. A set of reference trigger features is generated for each of the reference trigger nets. A net is selected from the netlist for each set of reference trigger features based on a similarity between the features of the net and the set of reference trigger features. The insertion netlist is generated that includes the circuit with the malicious design alteration inserted at each of the selected nets.

Systems and methods for machine intelligence based malicious design alteration insertion

A method and system for evaluating software tools that detect malicious hardware modifications is provided. In one embodiment, among others, a system comprises a computing device and an application. The application causes the computing device to at least receive hardware description language code that represents a circuit design and calculate a signal probability for one or more nodes in the circuit design. The application also causes the computing device to identify one or more rare nodes in the circuit design and generate a Trojan sample population. The application further causes the computing device to generate a feasible Trojan population and generate a Trojan test instance based at least in part on a random selection from the Trojan feasible population. Additionally, the application causes the computing device to generate modified hardware description code from the Trojan test instance.

Growing community of inventors

Gainesville, FL, United States of America

Jonathan William Cruz