Massachusetts Institute of Technology

Virtual Machine Works, Inc.

Jonathan William Babb

Ron Weiss

Thomas Knight

Anant Agarwal

Russell Tessier

Shuo Cory Li

Charles W Selvidge

Matthew L Dahl

Anant Argarwal

Adam Rubin

Michael Donald Noakes

Aspects of the invention relate to reconfigurable chassis that allow for rapid construction and optimization of biocircuits.

Bio-field programmable gate array and bio-programmable logic array: reconfigurable chassis construction

Aspects herein relate to composition, and related methods, for isolating and assembling DNA molecules without intermediate cloning steps.

Rapid assembly of multiple arbitrary length DNA fragments

A programmable logic circuit includes a programmable logic array which generates a plurality of output signals for output from a single port on the programmable logic circuit, and which processes a plurality of input signals received from a single port on the programmable logic circuit. The programmable logic circuit also includes multiplexing means for receiving the plurality of output signals generated by the programmable logic array and for multiplexing the plurality of output signals. An output port outputs, from the programmable logic circuit, the multiplexed plurality of output signals generated by the programmable logic array. An input port receives a multiplexed plurality of input signals, and a demultiplexing means demultiplexes the multiplexed plurality of input signals and configurably communicates the demultiplexed plurality of input signals to the programmable logic array. This demultiplexing means and the multiplexing means are each operable at a clock speed which is different from a clock speed of the programmable logic array.

Programmable multiplexing input/output port

Virtual interconnections for reconfigurable logic systems

A compilation technique overcomes device pin limitations using virtual interconnections. Virtual interconnections overcome pin limitations by intelligently multiplexing each physical wire among multiple logical wires and pipelining these connections at the maximum clocking frequency. Virtual interconnections increase usable bandwidth and relax the absolute limits imposed on gate utilization in logic emulation systems employing Field Programmable Gate Arrays (FPGAs). A 'softwire' compiler utilizes static routing and relies on minimal hardware support. The technique can be applied to any topology and FPGA device.

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Watertown, MA, United States of America

Jonathan William Babb