Taiwan Semiconductor Manufacturing Comp. Ltd.

Jonathan Tehan Chen

Chung-Cheng Chou

Po-Hao Lee

Yu-Der Chih

Chien-Yin Liu

Kuan-Chun Chen

Hsueh-Chih Yang

Kuo-Chi Tu

A method includes: retrieving a first word comprising a plurality of data bits and a plurality of parity bits that correspond to the first word, wherein the plurality of data bits form N&#x2212;1 groups and the plurality of parity bits form a first group different from the N&#x2212;1 groups, and N is a positive integer greater than 2; receiving a request to update respective data bits of a first one of the N&#x2212;1 groups; and providing a second word comprising updated data bits that form a second one of the N&#x2212;1 groups and a plurality of updated parity bits that correspond to the second word, wherein the plurality of updated parity bits form a second group that has a same group index as the first one of the N&#x2212;1 groups.

Memory device

The present disclosure provides resistive random access memory (RRAM) structures and methods of making the same. The RRAM structures include a bottom electrode having protruded step portion that allows formation of a self-aligned conductive path with a top electrode during operation. The protruded step portion may have an inclination angle of about 30 degrees to 150 degrees. Multiple RRAM structures may be formed by etching through a RRAM stack.

Resistive random access memory (RRAM) with improved forming voltage characteristics and method for making

A system and method of cooling a three dimensional integrated circuit (3D IC) using at least one thermoelectric cooler which is connected to the 3D IC by a plurality of conductive pillars. In some embodiments a controller controls power supply to the thermoelectric cooler, and a temperature monitor provides a temperature input to the controller. In some embodiments the controller maintains a temperature of a 3D IC within a predetermined range by cycling power to the thermoelectric cooler.

Cooling system for 3D IC

A device includes a memory bit cell, a first current source, and a current comparator electrically connected to the memory bit cell and the first current source. A first transistor has a first terminal electrically connected to a first voltage supply node, a control terminal electrically connected to a controller, and a second terminal electrically connected to the memory bit cell and the current comparator. A sense amplifier is electrically connected to the current comparator and a reference current generator.

Growing community of inventors

Hsinchu, Taiwan

Jonathan Tehan Chen