International Business Machines Corporation

Jonathan T Hsieh

Christian Jacobi

Khary J Alexander

Gregory William Alexander

James R Mitchell

Timothy John Slegel

Chung-Lung K Shum

Michael J Cadigan, Jr

Brian Robert Prasky

Brian William Thompto

James J Bonanno

Martin Recktenwald

Brian William Curran

Edward Thomas Malley

Dean G Bair

Yair Fried

Ariel Jonatan Birnbaum

Matthew G Pardini

Ilia Averbouch

Eugene S Rotter

Mark S Farrell

Anthony Saporito

Ute Gaertner

Adam B Collura

Eyal Naor

James Raymond Cuffney

Jang-Soo Lee

Yossi Shapira

Taylor J Pritchard

Charles Franklin Webb

Aaron Tsai

Jane Helen Bartik

Patrick M West, Jr

Ilya Granovsky

Aditya Nitin Puranik

Tu-An T Nguyen

Erez Barak

Michael P Mullen

Avraham Ayzenfeld

Deepankar Bhattacharjee

Olaf Knute Hendrickson

Richard Joseph Branciforte

Avery Francois

Matthew Michael Garcia Pardini

Gregory Miaskovsky

Shmuel Paycher

In an approach, responsibility for reissuing a fetch micro-operation is allocated to a reissue queue subsequent to a cache miss corresponding to a cache and the fetch micro-operation. Responsive to higher level cache returning data to the cache, an issue selection algorithm of the issue queue is overridden to prioritize reissuing the fetch micro-operation.

Load reissuing using an alternate issue queue

Methods, systems and computer program products for dynamically selecting an OSC hazard avoidance mechanism are provided. Aspects include receiving a load instruction that is associated with an operand store compare (OSC) prediction. The OSC prediction is stored in an entry of an OSC history table (OHT) and includes a multiple dependencies indicator (MDI). Responsive to determining the MDI is in a first state, aspects include applying a first OSC hazard avoidance mechanism in relation to the load instruction. Responsive to determining that the load instruction is dependent on more than one store instruction, aspects include placing the MDI in a second state. The MDI being in the second state provides an indication to apply a second OSC hazard avoidance mechanism in relation to the load instruction.

Dynamic selection of OSC hazard avoidance mechanism

A computer-implemented method for detecting vulnerabilities in microarchitectures. A non-limiting example of the computer-implemented method includes creating a simulation for execution on a model of a microarchitecture, the simulation including a set of instructions and a placeholder for holding a piece of secret data. The computer-implemented method executes the simulation a first time on the model of the microarchitecture with a first piece of secret data stored in the placeholder and stores a first output of the first executed simulation. The computer-implemented method executes the simulation a second time on the model of the microarchitecture with a second piece of secret data stored in the placeholder and stores a second output of the second executed simulation. The computer-implemented method compares the first output with the second output and provides an indication of a microarchitecture vulnerability when there is a difference between the first output and the second output.

Identifying microarchitectural security vulnerabilities using simulation comparison with modified secret data

Systems and methods of performing processor pipeline management include receiving an instruction for processing, determining that data in a first memory sub-group of a memory group needed to process the instruction is not available in a cache that ensures fixed latency access, and determining that the instruction should be put in a sleep state. The sleep state indicates that the instruction will not be reissued until the instruction is moved to a wakeup state. The methods also include associating the instruction with a ticket identifier (ID) that corresponds with a second memory sub-group of the memory group, and moving the instruction to the wakeup state based on the second memory sub-group of the memory group being moved into the cache.

Processor pipeline management during cache misses using next-best ticket identifier for sleep and wakeup

Examples of techniques for store hit multiple load side register for operand store compare are described herein. An aspect includes, based on detecting a store hit multiple load condition in the processor, updating a register of the processor to hold information corresponding to a first store instruction that triggered the detected store hit multiple load condition. Another aspect includes, based on issuing a second store instruction in the processor, determining whether the second store instruction corresponds to the information in the register. Another aspect includes, based on determining that the second store instruction corresponds to the information in the register, tagging the second store instruction with an operand store compare mark.

Store hit multiple load side register for preventing a subsequent store memory violation

Methods and systems for controlling writing to register files in a processing system having at least two execution pipelines are provided. Aspects include obtaining a micro operation for execution by an execution unit of a first pipeline in the processing system, wherein the micro operation includes writing data to a register file. Aspects also include determining whether the data will be accessed by an execution unit of a second pipeline in the processing system. Based on a determination that the data will only be accessed by the execution unit of the first pipeline, aspects include blocking writing of the data to a register file of the second pipeline.

Write power optimization for hardware employing pipe-based duplicate register files

Embodiments of the inventions are directed towards a computer-implemented methods and systems for determining an oldest logical memory address. The method includes creating an M number of miss request registers and an N number of stations in a load/store unit of the processor. In response to load requests from target instructions, a processor detects each L1 cache miss. The processor stores data related to each L1 cache miss in a respective miss request register. The data includes an age of each L1 cache miss and a portion of a logical memory address of the requested load. The processor stores the entire logical memory addresses of the requested loads in respective stations based on an age of the load requests. The processor transmits the oldest logical memory address that is stored at the stations.

Determining logical address of an oldest memory access request

Methods, systems and computer program products for monitoring delivered packages are provided. Aspects include receiving, by a co-processor, a data stream and performing processing on the data stream. Aspects also include writing, by the co-processor, a data record into the output buffer. Based on a determination that the data record should replace a most recently stored data record in a cache, aspects include providing, by the co-processor to the cache controller, an instruction for the cache controller to write the data record to a location in the cache obtained from a most recently used address register. Based on a determination that the data record should not replace the most recently stored data record in the cache, aspects include writing, by the cache controller, the data record to an available location in the cache.

Maintaining data order between buffers

Implementing processor instrumentation in a processor pipeline includes determining a pipeline depth of each micro-operator for an instruction group used in an execution phase of the processor pipeline. The pipeline depth corresponds with a duration of execution, each micro-operator performs a type of functional operation in the execution phase, and the instruction group includes all the micro-operators required for the execution phase. A targeted micro-operator is identified for which the processor instrumentation is being performed, and the pipeline depth corresponding with the targeted micro-operator is used to determine and report a performance of the targeted micro-operator as part of the processor instrumentation. Problems indicated by the processor instrumentation are diagnosed and addressed based on the performance of the targeted micro-operator.

Accounting for multiple pipeline depths in processor instrumentation

Provided are embodiments including a computer-implemented method, system and computer program product for determining precise operand-store-compare (OSC) predictions to avoid false dependencies. Some embodiments include detecting an instruction causing an OSC event, wherein the OSC event is at least one of a store-hit-load event or a load-hit-store event, marking an entry in a queue for the instruction based on the detected OSC event, wherein marking the entry comprises setting a bit and saving a tag in the entry in the queue. Some embodiments also include installing an address for the instruction and the tag in the history table responsive to completing the instruction.

Making precise operand-store-compare predictions to avoid false dependencies

A computer data processing system includes a plurality of logical registers, each including multiple storage sections. A processor writes data a storage section based on a dispatched first instruction, and sets a valid bit corresponding to the storage section that receives the data. In response to each subsequent instruction, the processor sets an evictor valid bit indicating a subsequent instruction has written new data to a storage section written by the first instruction, and updates the valid bit to indicate the storage section containing the new written data. A register combination unit generates a combined evictor tag to identify a most recent subsequent instruction. The processor determines the most recent subsequent instruction based on the combined evictor tag in response to a flush event, and unsets all the evictor tag valid bits set by the most the most recent subsequent instruction along with all previous subsequent instructions.

Imprecise register dependency tracking

A queue management capability enables allocation and management of tracking queue entries, such as load and/or store queue entries, at execution time. By introducing execution-time allocation of load/store queue entries, the allocation point of those entries is delayed further into the execution stage of the instruction pipeline, reducing the overall time the entry remains allocated to a specific instruction. The queue management capability may also resolve deadlock conditions resulting from execution-time allocation of the queue entries and/or provide a mechanism to avoid such deadlock conditions.

Delayed allocation of an out-of-order queue entry and based on determining that the entry is unavailable, enable deadlock avoidance involving reserving one or more entries in the queue, and disabling deadlock avoidance based on expiration of a predetermined amount of time

Embodiments relate to cache coherency verification using ordered lists. An aspect includes maintaining a plurality of ordered lists, each ordered list corresponding to a respective thread that is executed by a processor, wherein each ordered list comprises a plurality of atoms, each atom corresponding to a respective operation performed in a cache by the respective thread that corresponds to the ordered list in which the atom is located, wherein the plurality of atoms in an ordered list are ordered based on program order. Another aspect includes determining a state of an atom in an ordered list of the plurality of ordered lists. Another aspect includes comparing the state of the atom in an ordered list to a state of an operation corresponding to the atom in the cache. Yet another aspect includes, based on the comparing, determining that there is a coherency violation in the cache.

Cache coherency verification using ordered lists

A mechanism for simultaneous multithreading is provided. Responsive to performing a store instruction for a given thread of threads on a processor core and responsive to the core having ownership of a cache line in a cache, an entry of the store instruction is placed in a given store queue belonging to the given thread. The entry for the store instruction has a starting memory address and an ending memory address on the cache line. The starting memory addresses through ending memory addresses of load queues of the threads are compared on a byte-per-byte basis against the starting through ending memory address of the store instruction. Responsive to one memory address byte in the starting through ending memory addresses in the load queues overlapping with a memory address byte in the starting through ending memory address of the store instruction, the threads having the one memory address byte is flushed.

Load and store ordering for a strongly ordered simultaneous multithreading core

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Manchester, CT, United States of America

Jonathan T Hsieh