Micron Technology Incorporated

Nan Ya Technology Corporation

Jonathan T Doebler

Scott E Sills

Charles L Ingalls

Tae Hyoung Kim

Howard Kirsch

Kevin R Shea

Scott L Light

Lars P Heineck

Brett W Busch

Belford T Coursey

Mingtao Li

K Shawn Smith

Jennifer Lequn Liu

A semiconductor device comprises conductive lines, a conductive landing pad in electrical communication with a conductive line of the conductive lines, and a conductive interconnect structure in electrical communication with the conductive landing pad. The conductive interconnect structure comprises a contact plug in electrical communication with the conductive landing pad, and a global interconnect contact in electrical communication with the contact plug and having a greater lateral width than the contact plug. Related electronic systems and method are also disclosed.

Devices including conductive interconnect structures, related electronic systems, and related methods

The present invention is generally directed to a method of forming contacts for a memory device. In one illustrative embodiment, the method includes forming a layer of insulating material above an active area of a dual bit memory cell, forming a hard mask layer above the layer of insulating material, the hard mask layer having an original thickness, performing at least two partial etching processes on the hard mask layer to thereby define a patterned hard mask layer above the layer of insulating material, wherein each of the partial etching processes is designed to etch through less than the original thickness of the hard mask layer, the hard mask layer having openings formed therein that correspond to a digitline contact and a plurality of storage node contacts for the dual bit memory cell, and performing at least one etching process to form openings in the layer of insulating material for the digitline contact and the plurality of storage node contacts using the patterned hard mask layer as an etch mask.

Method of forming contacts for a memory device

Apparatuses, global and local wordline drivers, and methods for driving a wordline voltage in a memory is described. An example apparatus includes a memory array including a plurality of sub-arrays. The plurality of sub arrays are coupled to a wordline. The memory array further including a plurality of local wordline drivers coupled between a global wordline and the wordline. The plurality of local wordline drivers are configured to selectively couple the wordline to the global wordline during a memory access operation. The example apparatus further includes a global wordline driver configured to selectively couple the wordline to the global wordline during the memory access operation.

Apparatuses and methods for driving a voltage of a wordline of a memory

A method of forming capacitors includes providing a support material over a substrate. The support material is at least one of semiconductive or conductive. Openings are formed into the support material. The openings include at least one of semiconductive or conductive sidewalls. An insulator is deposited along the semiconductive and/or conductive opening sidewalls. A pair of capacitor electrodes having capacitor dielectric there-between is formed within the respective openings laterally inward of the deposited insulator. One of the pair of capacitor electrodes within the respective openings is laterally adjacent the deposited insulator. Other aspects are disclosed, including integrated circuitry independent of method of manufacture.

Integrated circuitry, methods of forming capacitors, and methods of forming integrated circuitry comprising an array of capacitors and circuitry peripheral to the array

An array includes a plurality of vertically-oriented transistors, rows of access lines, and columns of data/sense lines. Individual of the rows include an access line interconnecting transistors in that row. Individual of the columns include an inner data/sense line elevationally inward of the access lines and which interconnect transistors in that column. An outer data/sense line is elevationally outward of the access lines and electrically couples to the inner data/sense line. Other embodiments are disclosed, including memory arrays and memory cells.

Arrays of vertically-oriented transistors, memory arrays including vertically-oriented transistors, and memory cells

A method for forming patterns of dense conductor lines and their contact pads is described. Parallel base line patterns are formed over a substrate. Each of the base line patterns is trimmed. Derivative line patterns and derivative transverse patterns are formed as spaces on the sidewalls of the trimmed base line patterns, wherein the derivative transverse patterns are formed between the ends of the derivative line patterns and adjacent to the ends of the trimmed base line patterns. The trimmed base line patterns are removed. At least end portions of the derivative line patterns are removed, such that the derivative line patterns are separated from each other and all or portions of the derivative transverse patterns become patterns of contact pads each connected with a derivative line pattern.

Method for forming patterns of dense conductor lines and their contact pads, and memory array having dense conductor lines and contact pads

Devices having hybrid-vertical contacts. In certain embodiments, a substrate includes a lower patterned layer that has a target conductor. A hybrid-vertical contact may be disposed directly on the target conductor. The hybrid vertical contact may include a lower-vertical contact directly on the target conductor and an upper-vertical contact directly on the lower-vertical contact. The upper-vertical contact may have an upper width that is greater than a lower width of the lower-vertical contact.

Hybrid electrical contacts

Some embodiments include methods in which photolithographically-patterned photoresist features are used as templates during formation of a series of annular structures. The annular structures have linear segments. The linear segments are within a pattern having a pitch which is less than or equal to about half of a pitch of a pattern containing the photoresist features. An expanse of photoresist is formed across the annular structures. The expanse is photolithographically patterned to form chop patterns over ends of the annular structures, and to form at least one opening over at least one of the linear segments. The annular structures are etched while using the patterned photoresist expanse as a mask. In some embodiments, an opening in a photoresist expanse aligns to an edge of a linear segment through scum generated during photolithographic patterning of the photoresist expanse.

Methods of forming patterns

Techniques for manufacturing an electronic device. In certain embodiments, a substrate includes a lower patterned layer that has a target conductor. A hybrid-vertical contact may be disposed directly on the target conductor. The hybrid vertical contact may include a lower-vertical contact directly on the target conductor and an upper-vertical contact directly on the lower-vertical contact. The upper-vertical contact may have an upper width that is greater than a lower width of the lower-vertical contact.

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Boise, ID, United States of America

Jonathan T Doebler