Hitachi Data Systems Engineering UK Limited

Jonathan Soon Yew Teh

Simon Crosland

Andrew Peter Royal

Matthew Lester Hanham

Raymond Christopher Brown

Daniel James Nigel Picken

The apparatus includes: a hardware-side processing section including one or more programmable hardware-implemented chips configured to process request packets, which are received from host computers and relate to access requests to one or more file systems managed by the apparatus, and to generate response packets for the processed request packets; and a software-side processing section including one or more CPUs configured to execute decoding of requests packets sent from a host computer based on one or more computer programs stored in a memory of the software-side; wherein at least one programmable hardware-implemented chip of the hardware-side processing section is configured to process a credit request included in a received request packet, in particular without involvement of the software-side processing section.

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Basingstoke, United Kingdom

Jonathan Soon Yew Teh