Micron Technology Incorporated

Jonathan Scott Parry

Giuseppe Cariello

Timothy B Cowles

George B Raad

James S Rehmeyer

Nadav Grosz

David Aaron Palmer

Qing Liang

Reshmi Basu

Kishore Kumar Muchherla

Deping He

Christian M Gyllenskog

Stephen D Hanna

Liang Yu

Akira Goda

Kulachet Tanpairoj

Chun Sum Yeung

George Edward Pax

Luca Porzio

Jeffrey S McNeil, Jr

Jeremy Binfet

Sean L Manion

Stephen L Miller

Jung Sheng Hoei

Eric N Lee

Roberto Izzi

Niccolo' Righetti

Nicola Ciocchini

Nitul Gohain

Animesh Roy Chowdhury

Sivagnanam Parthasarathy

Violante Moschiano

Mustafa Nazmi Kaynak

Xiangang Luo

Michele Piccardi

Luigi Pilolli

Ugo Russo

Qisong Lin

Robert B Eisenhuth

Lakshmi Kalpana Vakati

George E Pax

Shuai Xu

Ashutosh Malshe

Jianmin Huang

Chang Hua Siau

Huai-Yuan Tseng

Michael Amiel Shore

Ting Luo

Xiaojiang Guo

Daniel J Hubbard

Suresh Rajgopal

Guang Hu

Silvia Beltrami

Niccolo′ Righetti

Yanhua Bi

Joseph A De La Cerda

Jameer Mulani

Bruce J Ford

Benjamin Rivera

Nicolas Soberanes

Ezra E Hartz

Sead Zildzic, Jr

Sead Zildzic

Chulbum Kim

Jeffrey Scott McNeil, Jr

Fumin Gu

John Paul Aglubat

Lakshmi Kalpana K Vakati

Gaspare Giglio

Patrick Miesen

Robert Loren O Ursua

A memory device includes memory dies, each memory die including a memory array and control logic, operatively coupled with the memory array, to perform peak power management (PPM) operations. The PPM operations include receiving a request to perform an operation, determining whether to initiate a PPM priority override procedure, and in response to determining to initiate the PPM priority override procedure, performing the PPM priority override procedure to execute the operation. Performing the PPM priority override procedure includes reconfiguring each high current breakpoints as a respective low current breakpoint to execute the operation.

Peak power management priority override

Methods, systems, and devices for topology-based retirement in a memory system are described. In some examples, a memory system or memory device may be configured to evaluate error conditions relative to a physical or electrical organization of a memory array, which may support inferring the presence or absence of defects in one or more structures of a memory device. For example, based on various evaluations of detected errors, a memory system or a memory device may be able to infer a presence of a short-circuit, an open circuit, a dielectric breakdown, or other defects of a memory array that may be related to wear or degradation over time, and retire a portion of a memory array based on such an inference.

Topology-based retirement in a memory system

In some implementations, a memory device may receive a write command that includes data to be written to the memory device. The memory device may receive an indication that single-level cell data caching is deactivated for the data. The memory device may determine whether the data is associated with a first data type or a second data type. The memory device may selectively write the data to single-level cell cache memory or multi-level cell main memory based on a determination of whether the data is associated with the first data type or the second data type and a determination of whether the single-level cell cache memory has available memory that is not reserved for the single-level cell data caching.

Opportunistic storage of non-write-boosted data in write booster cache memory

Methods, systems, and devices for write booster pinning are described. In some examples, a memory device may receive one or more commands (e.g., write commands) while operating in a first mode (e.g., a write booster mode). Some write commands may include an indication to pin the data to one or more SLCs. For example, a first write command may be associated with first data and a first indicator and a second write command may be associated with second data. Both the first data and the second data may be written to one or more SLCs. When maintenance operations are performed on the SLCs, the second data may be moved (e.g., written) to one or more MLCs. Additionally or alternatively, the memory system may receive one or more commands to unpin data (e.g., the first data) such that it may be moved to one or more MLCs during subsequent maintenance operations.

Write booster pinning

Methods, systems, and devices for storing parity during refresh operations are described. In some examples, refresh operations may be performed on a memory device when the memory device is idle. For example, a refresh operation may entail performing a logical operation on first data and a first set of parity bits and second data and a second set of parity bits. The logical operation may generate a third set of parity bits which may be used for data retention purposes. Moreover, during a read operation, the third set of parity bits may be used to recover corrupt or otherwise invalid data in the event of an error.

Storing parity during refresh operations

A memory die includes a memory array and control logic, operatively coupled with the memory array, to perform operations including receiving a peak power management (PPM) token during a current PPM cycle, in response to receiving the PPM token, determining, based on a set of communication frequencies, whether to communicate auxiliary data to at least one other memory die during the current PPM cycle, wherein each communication frequency of the set of communication frequencies indicates when a respective type of auxiliary data is eligible for communication during a PPM cycle, and in response to determining to communicate auxiliary data to the at least one other memory die, causing a selected type of auxiliary data to be communicated to the at least one other memory die, wherein the selected type of auxiliary data is determined from the set of communication frequencies in view of the current PPM cycle.

Scheduled interrupts for peak power management token ring communication

Methods, systems, and devices for low-power boot-up for memory systems are described. A memory system may be configured to receive, over a first conductive path of a second communication interface, a first indication to boot-up a memory system and a first communication interface associated with the memory system, wherein the first communication interface includes a plurality of conductive paths; receive, over a second conductive path of the second communication interface, a second indication whether to perform a boot-up operation of the memory system using a low-power mode or a high-power mode based at least in part on receiving the first indication; and boot the memory system according to the low-power mode or the high-power mode based at least in part on receiving the second indication.

Low-power boot-up for memory systems

Methods, systems, and devices for techniques for concurrent host system access and data folding are described. A memory system may determine to transfer (e.g., fold) data from a set of source data blocks to a set of destination data blocks. The memory system may receive a command to access a first source data block of the set of source data blocks concurrent with the data transfer. The memory system may generate a first order for transferring respective portions of the data that is based on a second order associated with a sequential read of the data from the set of destination data blocks. Based on the accessing the first source data block being concurrent with the data transfer, the first order may exclude a first portion of the data from the first source data block such that the data transfer and the accessing may be concurrently performed.

Techniques for concurrent host system access and data folding

A method performed by a processing device receives a plurality of write operation requests, where each of the write operation requests specifies a respective one of the memory units, identifies one or more operating characteristic values, where each operating characteristic value reflects one or more memory access operations performed on a memory device, and determines whether the operating characteristic values satisfy one or more threshold criteria. Responsive to determining that the operating characteristic values satisfy the one or more threshold criteria, the method performs a plurality of write operations, where each of the write operations writes data to the respective one of the memory units, and performs a multiple-read scan operation subsequent to the plurality of write operations, where the multiple-read scan operation reads data from each of the memory units.

Workload-based scan optimization

A memory device includes memory dies, each memory die including a memory array and control logic, operatively coupled with the memory array, to perform peak power management (PPM) operations. The PPM operations include causing a memory die to be placed in a suspended state to suspend execution of a first media access operation with a reserved current budget, receiving a set of requests to execute at least a second media access operation during the suspended state, and in response receiving the set of requests, handling the set of requests by implementing current budget arbitration logic with respect to the reserved current budget.

Peak power management in a memory device during suspend status

Provided herein are memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.

Methods for independent memory bank maintenance and memory devices and systems employing the same

Systems and methods of memory operation involving dynamic adjustment of write policy based on performance needs are disclosed. In one embodiment, an exemplary method may comprise monitoring memory performance parameters related to a programming operation being scheduled, selecting a write policy based on the memory performance parameters monitored, executing a memory control process that is configured to switch between the first addressing scheme and the second addressing scheme, and programming a first superpage of the programming operation using the first addressing scheme and programing a second superpage of the programming operation using the second addressing scheme.

Dynamic memory address write policy translation based on performance needs

A technique to provide power management for multiple dice. The technique provides for determining for each respective die of the multiple dice, power consumption for operating each respective die; and generating a respective signal from each respective die that corresponds to the power consumption of each respective die. The technique further provides for converting each respective signal to a respective analog voltage to drive a common node; and utilizing a charge storage device coupled to the common node to accumulate the respective analog voltages from the dice, where the accumulated voltage indicates total power consumption of the dice.

Charge-sharing capacitive monitoring circuit in a multi-chip package to control power

Apparatuses, systems, and methods for adapting a read disturb scan. One example method can include determining a delay between a first read command and a second read command, incrementing a read count based on the determined delay between the first read command and the second read command, and adapting a read disturb scan rate based on the incremented read count.

Adaptive read disturb scan

Methods, systems, and devices for adaptive throughput monitoring are described. In some examples, a memory system may be associated with one or more clocks that are each associated with a respective subcomponent. When the memory system receives a plurality of commands, the memory system may determine a throughput of the commands. Based on the determined throughput, the memory system may adjust a rate of one or more of the clocks.

Adaptive throughput monitoring

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Boise, ID, United States of America

Jonathan Scott Parry