Micron Technology Incorporated

Jonathan Scott Parry

Giuseppe Cariello

Nadav Grosz

Timothy B Cowles

George B Raad

James S Rehmeyer

David Aaron Palmer

Qing Liang

Kishore Kumar Muchherla

Reshmi Basu

Liang Yu

Deping He

Stephen D Hanna

Christian M Gyllenskog

Akira Goda

Kulachet Tanpairoj

Chun Sum Yeung

Luca Porzio

George Edward Pax

Jeffrey S McNeil, Jr

Jeremy Binfet

Jung Sheng Hoei

Nitul Gohain

Nicola Ciocchini

Sean L Manion

Animesh Roy Chowdhury

Stephen L Miller

Eric N Lee

Luigi Pilolli

Ugo Russo

Roberto Izzi

Niccolo' Righetti

Chulbum Kim

Sivagnanam Parthasarathy

Violante Moschiano

Mustafa Nazmi Kaynak

Xiangang Luo

Michele Piccardi

Daniel J Hubbard

Qisong Lin

Robert B Eisenhuth

Suresh Rajgopal

Jameer Mulani

Niccolo′ Righetti

Lakshmi Kalpana Vakati

George E Pax

Shuai Xu

Ashutosh Malshe

Jianmin Huang

Chang Hua Siau

Huai-Yuan Tseng

Michael Amiel Shore

Ting Luo

Xiaojiang Guo

David Scott Ebsen

Walter Di Francesco

Ali Mohammadzadeh

Tal Sharifie

Guang Hu

Silvia Beltrami

Yanhua Bi

Joseph A De La Cerda

Bruce J Ford

Benjamin Rivera

Nicolas Soberanes

Ezra E Hartz

Sead Zildzic, Jr

Luca Nubile

Biagio Iorio

Vivek Shivhare

Sead Zildzic

Jeffrey Scott McNeil, Jr

Fumin Gu

John Paul Aglubat

Lakshmi Kalpana K Vakati

Gaspare Giglio

Patrick Miesen

Hojung Yun

Robert Loren O Ursua

Methods, systems, and devices to enhance read performance for memory data word decoding using power allocation based on error pattern detection in both QLC and TLC in both QLC and TLC products are described. A plurality of data words may be processed using a first decoder engine of a decoder of a memory device according to a first power setting. The decoder may detect a pattern of errors in the plurality of data words. The decoder may further communicate a status signal based on detecting the pattern of errors. The resource manager may allocate based on the status signal, a second amount of power credits to the decoder. The decoder may process a portion of the plurality of data words using a second decoder engine according to the second amount of power credits.

Enhanced read performance for memory data word decoding using power allocation based on error pattern detection

A method includes receiving a request to perform a memory access operation, wherein the memory access operation includes a set of sub-operations, selecting a current quantization data structure from a plurality of current quantization data structures, wherein each current quantization data structure of the plurality of current quantization data structures maintains, for each sub-operation of the set of sub-operations, a respective current quantization value reflecting an amount of current that is consumed by the respective sub-operation based on a set of peak power management (PPM) operation parameters, and causing the memory access operation to be performed using PPM based on the current quantization data structure.

Multiple current quantization values for peak power management

Methods, systems, and apparatuses include allocating a temporary parity buffer to a parity group. A write command is received that includes user data and is directed to a portion of memory included in a zone which is included in the parity group. A memory identifier is determined for the portion of memory. Parity group data is received from the temporary parity buffer using the memory identifier. Updated parity group data is determined using the parity group data and the user data. The updated parity group data is sent to the temporary parity buffer.

Temporary parity buffer allocation for zones in a parity group

A memory device includes a set of memory dies, each memory die of the set of memory dies including a memory array and first control logic operatively coupled to the memory array, and an application-specific integrated circuit (ASIC) including a general-purpose input/output component (GPIO) including at least one digital pad communicably coupled to each memory die of the set of memory dies, and second control logic, operatively coupled to memory, to perform operations related to peak power management (PPM).

Peak power management extensions to application-specific integrated circuits

Methods, systems, and devices for shallow hibernate power state are described. A memory system may include a memory array and a controller. The memory system may transition from a first power state having a first current to a second power state having a second current less than the first current, where the first power state is associated with executing received commands and the second power state is associated with deactivating one or more components of the memory array. The memory system may initiate a timer after transitioning from the first power state to the second power state. The memory system may determine the timer satisfies a threshold and transition from the second power state to a third power state having a third current less than the second current based on the timer satisfying the threshold.

Shallow hibernate power state

A memory device includes memory dies. Each memory die includes a memory array and control logic, operatively coupled with the memory array, to perform operations for implementing peak power management (PPM) data burst communication. The operations include monitoring a data burst with respect to the memory array, detecting a current reservation trigger associated with the data burst, in response detecting the current reservation trigger, reserving an initial amount of current reflecting a maximum current consumption value associated with a maximum data transfer speed of the data burst, detecting a plurality of input/output cycles of the data burst following the preamble period, and in response to detecting the number of input/output cycles, reserving, based on an analysis of the plurality of input/output cycles, a subsequent amount of current reflecting an actual current consumption value associated with an actual data transfer speed of the data burst.

Peak power management data burst communication

A victim management unit (MU) for performing a media management operation is identified. The victim MU stores valid data in a first memory device of a plurality of memory devices. A cached data item on a second memory device of the plurality of memory devices is identified. A valid-to-invalid ratio of the victim MU is compared to a threshold value. In view of comparison, it is determined whether to pad the cached data item with at least a subset of the valid data stored at the victim MU or dummy data. Based on the determination, the cached data item padded with one of at least a subset of the valid data stored at the victim MU or the dummy data is written to a target MU.

Padding cached data with valid data for memory flush commands

A system includes a memory device including multiple memory cells and a processing device operatively coupled to the memory device. The processing device is to receive a first read command at a first time. The processing device is further to receive a second read command at a second time. The processing device is further to determine that the first read command and the second read command are directed to an at least partially same set of memory cells of the plurality of memory cells. The processing device is further to perform a media management operation with respect to the at least partially same set of memory cells.

Modified read counter incrementing scheme in a memory sub-system

Methods, systems, and devices for dual address encoding for logical-to-physical mapping are described. A memory device may identify a first physical address corresponding to a first logical block address generated by a host device and a second physical address corresponding to a second (consecutive) logical block address generated by a host device. The memory device may store the first physical address and second physical address in a single entry of a logical-to-physical mapping table that corresponds to the first logical block address. The memory device may transmit the logical-to-physical table to the host device for storage at the host device. The host device may subsequently transmit a single read command to the memory device that includes the first physical address and the second physical address based on the logical-to-physical table.

Dual address encoding for logical-to-physical mapping

A memory device includes memory dies, each memory die including a memory array and control logic, operatively coupled with the memory array, to perform peak power management (PPM) operations. The PPM operations include receiving a request to perform an operation, determining whether to initiate a PPM priority override procedure, and in response to determining to initiate the PPM priority override procedure, performing the PPM priority override procedure to execute the operation. Performing the PPM priority override procedure includes reconfiguring each high current breakpoints as a respective low current breakpoint to execute the operation.

Peak power management priority override

Methods, systems, and devices for topology-based retirement in a memory system are described. In some examples, a memory system or memory device may be configured to evaluate error conditions relative to a physical or electrical organization of a memory array, which may support inferring the presence or absence of defects in one or more structures of a memory device. For example, based on various evaluations of detected errors, a memory system or a memory device may be able to infer a presence of a short-circuit, an open circuit, a dielectric breakdown, or other defects of a memory array that may be related to wear or degradation over time, and retire a portion of a memory array based on such an inference.

Topology-based retirement in a memory system

In some implementations, a memory device may receive a write command that includes data to be written to the memory device. The memory device may receive an indication that single-level cell data caching is deactivated for the data. The memory device may determine whether the data is associated with a first data type or a second data type. The memory device may selectively write the data to single-level cell cache memory or multi-level cell main memory based on a determination of whether the data is associated with the first data type or the second data type and a determination of whether the single-level cell cache memory has available memory that is not reserved for the single-level cell data caching.

Opportunistic storage of non-write-boosted data in write booster cache memory

Methods, systems, and devices for write booster pinning are described. In some examples, a memory device may receive one or more commands (e.g., write commands) while operating in a first mode (e.g., a write booster mode). Some write commands may include an indication to pin the data to one or more SLCs. For example, a first write command may be associated with first data and a first indicator and a second write command may be associated with second data. Both the first data and the second data may be written to one or more SLCs. When maintenance operations are performed on the SLCs, the second data may be moved (e.g., written) to one or more MLCs. Additionally or alternatively, the memory system may receive one or more commands to unpin data (e.g., the first data) such that it may be moved to one or more MLCs during subsequent maintenance operations.

Write booster pinning

Methods, systems, and devices for storing parity during refresh operations are described. In some examples, refresh operations may be performed on a memory device when the memory device is idle. For example, a refresh operation may entail performing a logical operation on first data and a first set of parity bits and second data and a second set of parity bits. The logical operation may generate a third set of parity bits which may be used for data retention purposes. Moreover, during a read operation, the third set of parity bits may be used to recover corrupt or otherwise invalid data in the event of an error.

Storing parity during refresh operations

A memory die includes a memory array and control logic, operatively coupled with the memory array, to perform operations including receiving a peak power management (PPM) token during a current PPM cycle, in response to receiving the PPM token, determining, based on a set of communication frequencies, whether to communicate auxiliary data to at least one other memory die during the current PPM cycle, wherein each communication frequency of the set of communication frequencies indicates when a respective type of auxiliary data is eligible for communication during a PPM cycle, and in response to determining to communicate auxiliary data to the at least one other memory die, causing a selected type of auxiliary data to be communicated to the at least one other memory die, wherein the selected type of auxiliary data is determined from the set of communication frequencies in view of the current PPM cycle.

Scheduled interrupts for peak power management token ring communication

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Boise, ID, United States of America

Jonathan Scott Parry