Advanced Micro Devices Corporation

Fujitsu Corporation

Jonathan S Su

Colin Stewart Bill

Ravi Prakash Gutala

Sameer S Haddad

Ravi S Sunkavalli

Wing Han Leung

John Chen

Shane Charles Hollmer

Vei-Han Chen

Takao Akaogi

Chi K Chang

Lee Edward Cleveland

Pau-Ling Chen

Binh Quang Le

Vei-Han Chan

Yuan Tang

Chung K Chang

Chung-You Hu

Alexius H Tan

Qimeng (Derek) Zhou

Qimeng Derek Zhou

The present invention discloses a method and system to optimize electrical interconnection of electrical components in a periphery area of a memory device thereby minimizing the periphery area. The periphery area is divided into a plurality of sub-circuits formed by selectively electrically connecting the electrical components. Electrical interconnection of the electrical components to form the sub-circuits is accomplished using a first metal layer and a second metal layer. The first metal layer is formed to create a plurality of first metal layer lines that are oriented to extend in substantially one direction on the memory device. The second metal layer is formed to create a plurality of second metal layer lines that are oriented to extend substantially perpendicular to the first metal layer lines. The plurality of sub-circuits are electrically interconnected using a third metal layer that is formed to create a plurality of third metal layer lines that are oriented to extend substantially parallel to the first metal layer lines.

Three metal process for optimizing layout density

A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a plurality of field effect transistor memory cells, a power supply, and a controller which cooperates with the power supply to apply an erase pulse to the cells, and then erase verify a first byte of cells in each sector. If the first bytes in any sector has not passed erase verify, another erase pulse is applied to the cells of those sectors, and the first byte in each sector which did not pass erase verify the first time is erase verified again. This procedure is continued until the first byte in each sector has passed erase verify. Then, the sectors are processed in sequence to erase and erase verify every cell. First, an erase pulse is applied to all of the cells in the sector. Then, the first byte is erase verified. If the first byte passes erase verify (which it will because it did previously), the next byte is erase verified. Whenever a particular byte does not pass erase verify, another erase pulse is applied to all of the cells in the sector, and the particular cell is again erase verified. This procedure is sequentially performed on all of the bytes in the sector, or alternatively on the cells individually, until all of the cells have passed erase verify.

Method for erasing flash electrically erasable programmable read-only memory (EEPROM)

A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a plurality of floating gate transistor memory cells, a plurality of wordlines connected to the cells and a power supply for generating erase pulses. A controller controls the power supply to apply an erase pulse to all wordlines which are not deselected. Then, an erase verify procedure is applied to the cells in sequence. If all cells connected to a wordline pass the erase verify test, the wordline is deselected such that subsequent erase pulses will not be applied to the wordline and possibly cause the cells to become overerased. In one embodiment of the invention, erase verify is performed on all of the cells after an erase pulse is applied. The erase operation is completed when all cells pass erase verify. In another embodiment, erase verify is applied to each cell in sequence, with erase pulses being applied until each current cell passes erase verify. The wordlines can be deselected individually or in groups. The invention results in a tightening of the threshold voltage distribution of the cells.

Method for erasing flash electrically erasable programmable read-only

A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a plurality of floating gate transistor memory cells, a plurality of wordlines connected to the cells and a power source for generating a low power supply voltage on the order of 3 V or less. A wordline driver includes a booster for boosting the supply voltage to produce a wordline read voltage which is higher than the supply voltage, and applying the wordline voltage to a wordline. An upper clamp limits a maximum value of the wordline voltage to prevent read disturb. The upper clamp can be configured to reduce an amount by which the maximum value varies with the supply voltage, or to limit the maximum value to substantially a predetermined value. A lower clamp limits the wordline voltage to a minimum value which is higher than the supply voltage and lower than the maximum value for a predetermined length of time at the beginning of the read operation to ensure that the cells have sufficient read current and to reduce the amount by which the minimum value varies with the supply voltage.

Wordline driver for flash electrically erasable programmable read-only

An electrical rule check program takes simulation output files as input and performs an electrical rule check on the simulation to determine if any electrical design rules have been violated. The program scans a simulation output file to produce a subcircuit name list, an instance name list, and an internal index list for each subcircuit. If the number of circuit nodes is less than a first predetermined value, a window limit is set to equal the number of nodes times the number of data points. If the number of nodes is greater than the first predetermined value and less than a second predetermined value, then the window limit is set to equal some first predetermined fraction of the product of the number of nodes and the number of data points. If the number of nodes is greater than the second predetermined value, then the window limit is set to equal some second predetermined fraction of the product of the number of nodes and the number of data point, where the second predetermined fraction is less than the first predetermined fraction. The program then scans the simulation output file to produce an indexed node name list and a corresponding indexed voltage list to fill the window. The program performs the electrical rule checks and prints itemized report and statistics information. Each violation type supported by the electrical rule check program according to the present invention has a corresponding own violation output file. Currently supported rule types apply to junction breakdown, punch through, and gate oxide breakdown.

High voltage electrical rule check program

The present invention provides a method of verifying that all flash EEPROM transistors in a NAND string are properly erased without overerasing by applying a bias voltage to the source of the bottom select gate of the NAND array and applying a non-negative erase verify voltage to the control gates of each transistor during an erase verify. The bias voltage is at least equal to the erased threshold voltage of the worst case transistor to ensure proper erase verification. If all transistors are not erased, then another erase operation is performed. Erasing is repeated until the erase verify operation indicates that all transistors are properly erased. By erasing and verifying according to the present invention, the NAND array is completely and properly erased while minimizing overerasing the array.

Erase verify scheme for NAND flash

A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate, and a power source for supplying a plurality of voltages to the cells. A controller controls the power source to apply at least one erase pulse to the cells. Then, at least one overerase correction or 'soft programming' pulse is applied to the cells during which the source, drain and control gate voltages of the cells are such that the threshold voltages of overerased cells will be increased, but least erased cells will not be disturbed. The overerase correction pulses thereby tighten the threshold voltage distribution. A source to substrate bias voltage is applied for the duration of the overerase correction pulses which reduces the background leakage of the cells to a level at which the overerase correction operation can be effectively performed, even in applications with low supply voltages.

A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a semiconductor substrate, and a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate formed on the substrate. A controller controls a power source to apply an operational pulse to the drain of a cell, and apply a source to substrate bias voltage to the cell while the operational pulse is being applied thereto, the bias voltage having a value selected to reduce or substantially eliminate leakage current in the cell. The operational pulse can be an overerase correction pulse. In this case, a voltage which is substantially equal to the bias voltage is applied to the control gate for the duration of the overerase correction pulse. The operational pulse can also be a programming pulse. In this case, a voltage which is higher than the bias voltage is applied to the control gate of the selected wordline for the duration of the programming pulse. The bias voltage is preferably applied during both the overerase correction and programming pulses, reducing the power requirements and reducing the background leakage of the cells to a level at which program, read and overerase correction operations can be operatively performed.

Method for programming flash electrically erasable programmable

A timing apparatus for monitoring when a memory array in a non-volatile storage device needs to be refreshed includes a programmable semiconductor device and detecting means for detecting when the amount of charge on the programmable semiconductor device has diminished to at most a threshold amount. In one embodiment, the programmable semiconductor device is a floating gate transistor programmed by adding charge to the floating gate. The detecting means monitors the I.sub.DS current of the transistor and determines an array refresh time when more than a negligible amount of I.sub.DS current is detected.

Non-volatile storage device refresh time detector

An improved reading structure (110) for performing a read operation in an array of multiple bits-per-cell flash EEPROM memory cells is provided. A memory core array (12) includes a plurality of memory cells, each being previously programmed to one of a plurality of memory conditions defined by memory core threshold voltages. A reference cell array (22) includes a plurality of reference core cells which are selected together with a selected core cell and provides selectively one of a plurality of reference cell bit line voltages defined by reference cell threshold voltages. Each of the reference cells are previously programmed at the same time as when the memory core cells are being programmed. A precharge circuit (36) is used to precharge the array bit lines and the reference bit lines to a predetermined potential. A detector circuit (28) is responsive to the bit line voltages of the reference cells for generating strobe signals. A reading circuit (26) is responsive to the strobe signals for comparing the memory core threshold voltage with each of the reference cell threshold voltages.

Bit line discharge method for reading a multiple bits-per-cell flash

A shift register page buffer for use in an array of multiple bits-per-cell flash EEPROM memory cells so as to render page mode programming and reading is provided. A sensing logic circuit (26,27) is used to selectively and sequentially compare array bit line voltages with each of a plurality of target reference cell bit line voltages. Shift register circuit (300) is responsive to the sensing logic circuit for sequentially storing either a low or high logic level after each comparison of the bit line voltages with one of the plurality of target reference voltages. Each of the shift register circuits is formed of series-connected latch circuits (302-308), each having inputs and outputs. A switching transistor (N5) is interconnected between the sensing logic circuit and the latch circuits and is responsive to a corresponding output of the latch circuits for selectively passing the logic signal from the sensing circuit means to the input of the latch circuits.

Multiple bits-per-cell flash shift register page buffer

An improved erasing structure for performing a programming back operation and a concurrent verify operation subsequent to application of an erasing pulse in an array of multiple bits-per-cell flash EEPROM memory cells is provided. A memory core array (12) includes a plurality of memory cells and an erase verify reference cell array for generating an upper erased state threshold voltage level. A pre-charge circuit (36a) is used to pre-charge all the array bit lines to a predetermined potential prior to a programming back operation. A reference generator circuit (134) is used for generating a reference output voltage corresponding to a lower erased state threshold voltage level. A switching circuit (P1, N1) is used to selectively disconnect a program current source of approximately 5 .mu.A from the selected certain ones of the columns of array bit lines containing the selected memory core cells which have been correctly programmed back. A sense logic circuit (26, 27) continuously compares a potential on one of the selected bit lines and the reference output voltage corresponding to the lower erase threshold voltage level. The sensing logic circuit generates a logic signal which is switched to a low logic level when the potential on the selected bit line falls below the bit line voltage corresponding to the lower erased state threshold voltage level. The switching circuit is responsive to the low logic level for disconnecting the programming current source so as to inhibit further programming back of the selected memory core cells.

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Evanston, IL, United States of America

Jonathan S Su