Texas Instruments Corporation

Jonathan S Brodsky

Robert Steinhoff

John Eric Kunz, Jr

Thomas A Vrotsos

Sameer P Pendharkar

Gianluca Boselli

David John Baldwin

Timothy Patrick Pauletti

Wayne Tien-Feng Chen

Joseph A Devore

Lin Chen

Dening Wang

Wei-Chung Wu

Wenliang Chen

Yuan Gu

Sameer Pendharker

An electrostatic discharge (ESD) device for protecting an input/output terminal of a circuit, the device comprising a first transistor with an integrated silicon-controlled rectifier (SCR) coupled between the input/output (I/O) terminal of the circuit and a node and a second transistor with an integrated silicon-controlled rectifier coupled between the node and a negative terminal of a supply voltage, wherein the silicon-controlled rectifier of the first transistor triggers in response to a negative ESD voltage and the silicon-controlled rectifier of the second transistor triggers in response to a positive ESD voltage.

Bi-directional ESD protection circuit

An integrated circuit may include an over-capability detection circuit coupled to an I/O pad which provides a shut-off signal to a latch controlling an ESD protection shunting component. The ESD protection shunting component is coupled between the I/O pad and a reference node of the integrated circuit. The over-capability detection circuit provides the shut-off signal when safe operating conditions are resumed after a voltage excursion at the I/O pad. After receiving the shut-off signal, the latch biases the ESD protection shunting component into an off-state.

Shut-off circuits for latched active ESD FET

An ESD monitor device may take the form of an integrated circuit with a plurality of monitor components available at each I/O site of the ESD monitor device. Each monitor component has a physical structure which provides scalable ESD robustness. The monitor components are connected in parallel to an ESD bus. An integrated circuit may be formed by processing an ESD monitor device through one or more process steps of an integrated circuit manufacturing line, and subsequently measuring the ESD monitor device. Parameters of a process step of the manufacturing line may be adjusted to reduce ESD events at the process step, based on measurement results from the ESD monitor device. The integrated circuit may subsequently be processed through the adjusted process step.

Packaged device for detecting factory ESD events

An integrated circuit with either a normally open MEMS ESD protection switch coupled between a bond pad and an internal circuit or a normally closed MEMS ESD protection switch coupled between the bond pad and a common reference of the integrated circuit. At least one of a control bond pad and an enable logic circuit is coupled to a control terminal of the MEMS ESD protection switch.

Static MEMS switch for ESD protection

A structure is designed with an external terminal () and a reference terminal (). A first transistor () is formed on a substrate. The first transistor has a current path coupled between the external terminal and the reference terminal. A second transistor () has a current path coupled between the external terminal and the substrate. A third transistor () has a current path coupled between the substrate and the reference terminal.

Bi-directional electrostatic discharge (ESD) protection circuit

An active-FET ESD cell () for protecting an I/O pad () includes a first MOS transistor () with a gate oxide () of a first thickness and a second MOS transistor () with a gate oxide () of a second thickness greater than the first thickness at least by the amount required to handle the source-follower threshold voltage, the first transistor having its drain () tied to the I/O pad, its source () tied to ground, and its gate () tied to the source () of the second transistor and resistively connected to ground (), and the second transistor having its drain () tied to the I/O pad and its gate tied to a capacitor () connected to the I/O pad and to a resistor () connected to ground.

Electrostatic discharge protection circuit having buffer stage FET with thicker gate oxide than common-source FET

Disclosed is an electrostatic discharge (ESD) protection validator, a method of validating ESD protection for an IC and an ESD validation system. In one embodiment, the ESD protection validator includes: (1) a circuit analyzer configured to compare component information of the IC with predefined ESD protection elements to identify ESD cells of the IC and (2) an ESD cell verifier configured to compare physical attributes associated with the identified ESD cells to ESD protection requirements and determine compliance therewith.

ESD protection validator, an ESD validation system and a method of validating ESD protection for an IC

A modeler for components of an IC under ESD conditions, a method of simulating ESD behavior of an IC and an ESD simulation system. In one embodiment, the modeler includes: (1) a circuit analyzer configured to provide identified ESD cells and circuitry of the IC by comparing component information of the IC with predefined ESD protection elements and predefined circuit topologies and (2) a model generator configured to create linearized models of the identified ESD cells and the identified circuitry based on physical attributes associated with the identified ESD cells and the identified circuitry, wherein a combination of the linearized models represent operation of the IC component under ESD conditions.

System, an apparatus and a method for performing chip-level electrostatic discharge simulations

An ESD protection optimizer, a method of optimizing ESD protection for an IC and an ESD protection optimization system is disclosed. In one embodiment, the ESD protection optimizer includes: (1) a circuit analyzer configured to identify ESD cells and circuitry of the IC by comparing component information of the IC with predefined ESD protection elements and predefined circuit topologies and (2) an ESD resistance determiner configured to calculate a resistance value to couple in series with the circuitry, the resistance value based on protection cell physical attributes associated with the identified ESD cells and circuitry physical attributes associated with the identified circuitry.

Method of optimizing ESD protection for an IC, an ESD protection optimizer and an ESD protection optimization system

Various apparatuses, methods and systems for protecting a driver from electrostatic discharge are disclosed herein. For example, some exemplary embodiments provide a driver, including a buffer, a leakage path blocking transistor connected to an output of the buffer, and an output driver connected to an output of the leakage path blocking transistor. Current from the output driver to the buffer is substantially blocked by the leakage path blocking transistor.

Driver with electrostatic discharge protection

A semiconductor device includes one or more LDMOS transistors and one of more SCR-LDMOS transistors. Each LDMOS transistor includes a LDMOS well of a first conductivity type, a LDMOS source region of a second conductivity type formed in the LDMOS well, and a LDMOS drain region of a second conductivity type separated from the LDMOS well by a LDMOS drift region of the second conductivity type. Each SCR-LDMOS transistor comprising a SCR-LDMOS well of the first conductivity type, a SCR-LDMOS source region of the second conductivity type formed in the SCR-LDMOS well, a SCR-LDMOS drain region of a second conductivity type, and a anode region of the first conductivity type between the SCR-LDMOS drain region and the SCR-LDMOS drift region. The anode region is separated from the SCR-LDMOS well by a SCR-LDMOS drift region of the second conductivity type.

Growing community of inventors

Plano, TX, United States of America

Jonathan S Brodsky