Cisco Technology, Inc.

Jonathan Rosen

Dean Hiller

Mark C Drummond

Robert O'Gorman

Earl T Cohen

John Andrew Fingerhut

Feng Cao

Stephen Charles Hilla

Harikrishnan Pillai

Donald Edward Steiss

Shuxian Lou

John Joseph Williams, Jr

Jie Chu

Kenneth H Potter

Barry Scott Burns

William P Brandt

Christopher E White

Douglas Michael Toney

Paul A Wood

Clifford B Melzer

Ibrahim Delibalta

John J Williams

Intelligent distribution of packet flows may be provided. Compute resource data may be received. Next, packets may be classified into flows that may be persistently mapped to compute resources for a lifetime of the flows. Based on the compute resource data, the flows may then be allocated to the compute resources.

Intelligent packet distribution control for optimizing system performance and cost

Techniques and mechanisms for IPsec processing of IPsec packets for routing platforms where IPsec is just one or more features in the middle of data path features on the packet processing path and hence, the typical, simple inline IPsec scheme does not work well for such platforms. The techniques include using a hardware look-up table for packet classification and inbound security association (SA) lookup in one pass with IP 5-tuple plus SPI as a lookup key at hardware table. The techniques provide an entry match action format and mechanism for deriving inbound SA dram addresses that may be used by a hardware (HW)/firmware (FW) crypto/IPsec engine to process inbound packet traffic. A software SA look-up table is also provided to overcome hardware look-up table resource limitations and support more IPsec session scaling than the physical hardware look-up table can handle. Additional techniques are described.

IPsec processing of packets in SoCs

A processing engine includes descriptor transfer logic that receives descriptors generated by a software controlled general purpose processing element. The descriptor transfer logic manages transactions that send the descriptors to resources for execution and receive responses back from the resources in response to the sent descriptors. The descriptor transfer logic can manage the allocation and operation of buffers and registers that initiate the transaction, track the status of the transaction, and receive the responses back from the resources all on behalf of the general purpose processing element.

Descriptor transfer logic

A processing device employs a stack memory in a region of an external memory. The processing device has a stack pointer register to store a current top address for the stack memory. One of several techniques is used to determine which portion or portions of the external memory correspond to the stack region. A more efficient memory policy is implemented, whereby pushes to the stack do not have to read data from the external memory in to a cache, and whereby pops from the stack do not cause stale stack data to be written back from the cache to the external memory.

Optimizing cached access to stack storage

A resource unit has a request interface to allow the unit to receive a request and associated data. The resource unit also has a hashing engine to create a hash of the associated data, a modulo engine to create a modulus result, a read engine to perform a memory read, and a results interface to allow the device to return results.

Hashing assist for network processors

Data is protected using locks, with the protected data sometimes being included in the locking messages, which may reduce overall processing latency, and/or reduce a bandwidth requirement for and/or number of storage operations accessing the native storage of the protected data. For example, the lock manager receives lock requests from each of the requesters, and selectively grants the lock requests. The protected data is typically communicated in the locking messages when the lock is highly contested, or at least two request for access to the data are pending. The lock manager initiates the sequence by indicating in a grant message to a requester to include the protected data in its release message. The lock manager then copies this data received in the release message to its grant message to the next requestor. If no other requesters are waiting, the grant message includes an indication not to send the protected data, and thus the requestor typically stores this protected data to storage so it can be accessed in the future.

Bypassing native storage operations by communicating protected data within locking messages using a lock manager independent of the storage mechanism

A mapping technique allows a forwarding engine of an intermediate node to efficiently compute a starting address within an internal packet memory (IPM) configured to hold a packet received at the node. The starting address is used by direct memory access logic to merge a trailer of the packet stored in the IPM with a modified packet header generated by the forwarding engine. However, the size of the IPM is preferably not a binary number that can be easily manipulated by the forwarding engine when computing the starting address of the packet within the IPM. Therefore, the technique automatically adjusts the starting address to map to a correct location if the address exceeds the size of the IPM, while obviating the need for the forwarding engine to consider a wrap-around condition when computing the starting address.

Mapping technique for computing addresses in a memory of an intermediate network node

An option request protocol allows dynamic negotiation of options between a host computer and a control unit of a computer network. The protocol is manifested as an exchange of novel control messages over a control link used to establish logical data links for communication between the host and control unit. The options negotiated by the control message exchange generally pertain to additional functions performed by the control unit or host, or additional parameters for communication over the data links coupling the control unit and host.

Option request protocol

A cache blocking mechanism ensures that transient data is not stored in a secondary cache of a router by managing a designated set of buffers in a main memory of the router. The mechanism defines a window of virtual addresses that map to predetermined physical memory addresses associated with the set of buffers; in the illustrative embodiment, only transient data may be stored in these buffers. The mechanism further blocks write requests directed to these predetermined memory buffers from propagating to the secondary cache, thereby precluding storage of transient data in the cache.

Cache blocking of specific data to secondary cache with a first and a second OR circuit

A technique allows dynamic negotiation of application names executing on nodes of a computer network for creating a data link for communication between the nodes. Dynamic negotiation is effected through an exchange of novel control messages over a control link used to establish application-application logical links between the nodes. The control messages instruct the nodes to create applications having names specified within predetermined fields of the messages. The technique obviates the need for a system administrator to issue configuration commands to a responding node to statically configure that latter node for communication over a network.

Method and apparatus for dynamic link name negotiation

Secondary cache write-through blocking mechanism

A technique enables a control unit to perform checksum operations for packets, which operations are otherwise performed by a host computer of a computer network. The technique involves the use of two data links coupled between the host and control unit; one data link is used for exchanging 'normal' IP packets without checksum operations performed thereon by the control unit and the other link is used for exchanging IP packets that have undergone or will undergo checksum operations by the control unit. By 'offloading' checksum operations to the control unit, the technique reduces processor cycles consumed by the host, thereby improving the performance of the host computer and network.

Growing community of inventors

Cary, NC, United States of America

Jonathan Rosen