Lenovo (singapore) Pte. Ltd.

Sanmina-sci Corporation

International Business Machines Corporation

Lenovo Global Technology (united States) Inc.

Lenovo Enterprise Solutions (singapore) Pte. Ltd.

Sanmina Corporation

Jonathan Randall Hinkle

David W Cosby

Paul Sweere

Michael Neil Condict

Theodore Brian Vojnovich

Justin Potok Bandholz

Patrick Leo Caporale

Jason Aaron Matteson

Shigefumi Odaohhara

Pravin S Patel

Jose M Orro

Makoto Ono

Fred Allison Bower, Iii

Paul Andrew Wormsbecher

William Gavin Holland

Caihong Zhang

Kevin Michael Reinberg

Tony Carl Sass

Ming Lei

Randolph Scot Kolvick

Derek Ian Schmidt

Clifton Ehrich Kerr

Jiang Chen

Andrew Thomas Junkins

William James Sommerville

Yasushi Honda

John Frank Nations, Jr

Shiro Konaka

Devarshi S Patel

A far memory device includes a far memory controller, a memory device coupled to the controller, a first port coupled to the far memory controller to support communication with a host processor over a first serial computer expansion bus, and a second port coupled to the far memory controller to support communication with a non-volatile data storage drive over a second serial computer expansion bus. The far memory device serves as a cache between the host processor and the non-volatile data storage drive and may perform aspects of cache management on behalf of the host processor.

Far memory direct caching

An apparatus includes a plurality of data buffer and multiplexer devices that communicate data signals with the host memory controller at twice the clock rate that the data buffer and multiplexer devices communicate first and second data signals with first and second memory modules. The apparatus further includes a registered clock driver that communicates host command and address signals at twice the clock rate that the registered clock driver communicates first and second command and address signals with the first and second memory modules. The second data signals and second command and address signals may be directed to a data conversion module that converts the signals to be communicated over a serial computer expansion bus with the second memory module.

Multi-access memory modules

A computer-implemented method and a serially-attached memory device for performing the method are provided. The method includes a memory device controller receiving data over an error-protected serial link from a host processor, wherein the memory device controller is included in a serially-attached memory device along with memory media coupled to the memory device controller. The method further includes the memory device controller storing the received data in the memory media coupled to the memory device controller, the memory device controller calculating error correction code for the received data, and the memory device controller storing the error correction code in the memory media coupled to the memory device controller.

Error correction code offload for a serially-attached memory device

A dynamic random-access memory array includes a plurality of memory cells and sensor cells physical arranged in a row. The sensor cells include a transistor and a capacitor having an input terminal connected to a first non-gate terminal of the transistor. A wordline is connected to transistor gates of both the memory cells and sensor cells in the row. A sensor amplifier has inputs connected to the sensor cell, a high voltage reference line, and a low voltage reference line, and an output in communication with a row refresh circuit. If the sensor amplifier detects that the sensor cell voltage falls outside of the range of the high and low voltage reference lines, then a trigger signal is output to request that the row refresh circuit perform a priority row refresh of the memory cells and the sensor cell in the row.

Dynamic random-access memory array including sensor cells

A computer program product provides program instructions that are executable by a processor to cause the processor to perform various operations. The operations may include monitoring a performance metric for a workload instance being executed by a composed system within a pool of composable resources in a composable computing system. The composed system includes a compute resource and an associated hardware resource selected from a data storage resource, a memory resource and/or a graphic processing resource. A service level agreement is identified for the workload instance, wherein the agreement includes a minimum level of the performance metric that the composed system must provide to support the workload instance. A power cap may be imposed on the compute resource, and a power cap may be imposed on the associated hardware resource by sending a power capping command to a baseboard management controller on a server including the associated hardware resource.

Power capping in a composable computing system

Powering random access memory (RAM) modules with non-volatile memory components may include providing, by a power supply, a first output voltage to one or more RAM modules, each RAM module of the one or more RAM modules comprising a volatile memory component and a non-volatile memory component; providing, by the power supply, a second output voltage to one or more system components distinct from the one or more RAM modules; detecting a power event; sending, by the power supply, in response to detecting the power event, a signal to the one or more RAM modules to initiate a save operation, wherein the save operation comprises storing, for each of the one or more RAM modules, data from the volatile memory component to the non-volatile memory component; and ceasing, by the power supply, the second output voltage while maintaining the first output voltage to facilitate the save operation.

Powering random access memory modules with non-volatile memory components

An apparatus for secure multiple server access to a non-volatile storage device is disclosed. A method and storage device product also perform the functions of the apparatus. An apparatus includes a storage device with three or more ports. Each port includes at least one lane and each port is configured to connect to a different server over the at least one lane of the port. The storage device includes a storage controller in the storage device for each port. Each storage controller controls storage to non-volatile storage of the storage device. The storage device includes a logical namespace assigned to each port. Each logical namespace is assigned to a portion of the non-volatile storage of the storage device. The logical namespace of a first port of the three or more ports is inaccessible to a second port of the three or more ports.

Secure multiple server access to a non-volatile storage device

A storage area network (SAN) includes fabric-attachable storage drives that are each directly connected to a fabric and that operate drive volumes. The SAN includes SAN software agents executed by client computing devices that are directly connected to the fabric. Each SAN software agent operates logical volumes realized by the drive volumes of the storage drives. The SAN includes a SAN manager directly connected to the fabric to manage the drive volumes of the SAN storage drives and to manage the logical volumes that the SAN software agents operate.

Storage area network having fabric-attached storage drives, SAN agent-executing client devices, and SAN manager that manages logical volume without handling data transfer between client computing device and storage drive that provides drive volume of the logical volume

An apparatus includes a root port for coupling to a root complex, and a plurality of endpoint ports for coupling to endpoint devices, wherein each endpoint port is associated with a function number. A downstream buffer queues transaction layer packets (TLPs) received from the root port, wherein each TLP in the downstream buffer is directed to an endpoint port associated with the identified function number. An upstream buffer queues TLPs received from each endpoint port, and directs the queued TLPs to the root port. A method includes associating a function number with each endpoint port of a switch, wherein each endpoint port is adapted for coupling to an endpoint device. The method further includes receiving a first TLP from a root complex, identifying a function number within the first TLP, and directing the first TLP to an endpoint device through the endpoint port associated with the identified function number.

PCIe switch for aggregating a large number of endpoint devices

An apparatus for cache coherency between a device and a processor includes a buffer module that buffers data in a non-cache coherent space of an electronic device communicatively coupled to a processor. The apparatus includes an update module that updates at least one identifier with respect to the buffered data. The at least one identifier is stored in a cache coherent space of the electronic device. The apparatus includes a coherence notification module that notifies the processor of a cache incoherence. The cache incoherence indicates that the cache coherent space of the electronic device that includes the updated at least one identifier differs from a cache coherent space of the processor that includes a copy of the at least one identifier prior to the update.

Cache coherency between a device and a processor

One embodiment provides a method, including: identifying, using a processor, a connection of a device to an information handling device; receiving, at the information handling device, an indication of a user selection action on the device; and performing, responsive to receiving the indication, an action on the information handling device. Other aspects are described and claimed.

Connected device activation

Disclosed are methods and systems for low latency modification of memory on a remote computer system. According to one aspect of the present disclosure, a method includes, at a first computing device, receiving from a second computing device, a memory access request including a security key and a unique identifier generated by the first computing device. The method further includes verifying, based on the security key and the unique identifier, that the first computing device is authorized to access a predetermined portion of memory. Also, in response to verifying that the first computing device is authorized to access the predetermined portion of memory, accessing, by the second computing device, the predetermined portion of memory.

Systems and methods for low latency access of memory between computing devices

A method for improving safety of voltage regulator is disclosed. In order to improve safety of a voltage regulator, a MOS-FET is disposed on a source power lane that receives power supplied from a DC power supply. A set of voltage regulators is connected to a set of fork power lanes, correspondingly, branching off from the source power lane. PTC thermistors are disposed on a surface or in the vicinity of semiconductor chips of the voltage regulators. When temperature at any one of the PTC thermistors increases, a protection controller turns off the MOS-FET. When temperature detected by a temperature sensor incorporated within the semiconductor chip has increased, each of the voltage regulators turns off the MOS-FET via a base management controller.

Method for improving safety of voltage regulator

A method, computer program product and apparatus are provided. For example, the method includes receiving, by a first data storage device within a storage area network, input output operations over a first network pathway within the storage area network. The method further includes receiving, by the first data storage device, a migration instruction that identifies a second data storage device within the storage area network and a source volume stored on the first data storage device. Still further, the method includes migrating, by the first data storage device, the source volume directly to the second data storage device over a second network pathway within the storage area network.

Growing community of inventors

Raleigh, NC, United States of America

Jonathan Randall Hinkle