Tela Innovations, Inc.

Jonathan R Quandt

Scott T Becker

Dhrumil Gandhi

Michael C Smayling

Daryl Fox

Carole Lambert

Jim Mali

A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists between the first and second virtual grates. A number of cells are placed within the logic block area. Each of the number of cells is defined according to an appropriate one of a number of cell phases. The appropriate one of the number of cell phases causes layout features in the first and second chip levels of a given placed cell to be aligned with the first and second virtual grates as positioned within the given placed cell.

Methods for cell phasing and placement in dynamic array architecture and implementation of the same

A method is disclosed for defining an integrated circuit. The method includes generating a digital data file that includes both electrical connection information and physical topology information for a number of circuit components. The method also includes operating a computer to execute a layout generation program. The layout generation program reads the electrical connection and physical topology information for each of the number of circuit components from the digital data file and automatically creates one or more layout structures necessary to form each of the number of circuit components in a semiconductor device fabrication process, such that the one or more layout structures comply with the physical topology information read from the digital data file. The computer is also operated to store the one or more layout structures necessary to form each of the number of circuit components in a digital format on a computer readable medium.

Scalable meta-data objects

A semiconductor device includes a plurality of cells. Each of the cells has a respective outer cell boundary defined to circumscribe the cell in an orthogonal manner. Also, each of the cells includes circuitry for performing one or more logic functions. This circuitry includes a plurality of conductive features defined in one or more levels of the cell. One or more of the conductive features in at least one level of a given cell is an encroaching feature positioned to encroach by an encroachment distance into an exclusion zone. The exclusion zone occupies an area within the cell defined by an exclusion distance extending perpendicularly inward into the given cell from a first segment of the outer cell boundary. The exclusion distance is based on a design rule distance representing a minimum separation distance required between conductive features in adjacently placed cells on the semiconductor device.

Methods for cell boundary encroachment and semiconductor devices implementing the same

A semiconductor device is disclosed to include a plurality of cells. Each of the cells has a respective outer cell boundary defined to circumscribe the cell in an orthogonal manner. Also, each of the cells includes circuitry for performing one or more logic functions. This circuitry includes a plurality of conductive features defined in one or more levels of the cell. One or more of the conductive features in at least one level of a given cell is an encroaching feature positioned to encroach by an encroachment distance into an exclusion zone. The exclusion zone occupies an area within the cell defined by an exclusion distance extending perpendicularly inward into the given cell from a first segment of the outer cell boundary. The exclusion distance is based on a design rule distance representing a minimum separation distance required between conductive features in adjacently placed cells on the semiconductor device.

Methods for cell boundary encroachment and layouts implementing the same

A first transistor has source and drain regions within a first diffusion fin. The first diffusion fin projects from a surface of a substrate. The first diffusion fin extends lengthwise in a first direction from a first end to a second end of the first diffusion fin. A second transistor has source and drain regions within a second diffusion fin. The second diffusion fin projects from the surface of the substrate. The second diffusion fin extends lengthwise in the first direction from a first end to a second end of the second diffusion fin. The second diffusion fin is positioned next to and spaced apart from the first diffusion fin. Either the first end or the second end of the second diffusion fin is positioned in the first direction between the first end and the second end of the first diffusion fin.

Circuits with linear finfet structures

A first gate level feature forms gate electrodes of a first finfet transistor of a first transistor type and a first finfet transistor of a second transistor type. A second gate level feature forms a gate electrode of a second finfet transistor of the first transistor type. A third gate level feature forms a gate electrode of a second finfet transistor of the second transistor type. The gate electrodes of the second finfet transistors of the first and second transistor types are electrically connected to each other. The gate electrodes of the second finfet transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first finfet transistors of the first and second transistor types are positioned.

Growing community of inventors

San Jose, CA, United States of America

Jonathan R Quandt