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Infineon Technologies Richmond, LP

Infineon Technologes Richmond, LP

Jonathan Philip Davis

Michael Rennie

Robert T Fuller

Scott William Bailey

Joseph Page

Francis Goodwin

Daniel Bernard Ruskin

Stephen M Rusinko, Jr

A non-volatile computer readable medium is disclosed comprising computer program instructions that, when executed by at least one hardware processor, configure the at least one hardware processor to: display a ballot to a voter; collect candidate selections from a voter; and generate an encrypted ballot variant and a plaintext ballot variant. Corresponding systems and methods are also disclosed.

Voting booth, system, and methods of making and using same

A processing sequence for definition of gate contacts can be implemented using either a deep ultra-violet (DUV) or mid ultra-violet (MUV) positive resist processing and supports the use of a reticle that integrates contacts to various regions including gates, sources and drains of various devices. In a one example, the wafer is coated with a planarizing anti-reflective coating (ARC), which then supports imaging of gate contacts using a positive DUV or MUV resist. This processing allows the nitride cap of certain transistor gates to be replaced with an oxide. In this example, the ARC can serve as an etch guide for selective removal of a film.

Method of forming a gate contact in a semiconductor device

A semiconductor memory device comprises a trench etched from a substrate below a shallow trench isolation and a doped collar oxide. The device further comprises a buried-strap junction formed adjacent to the shallow trench isolation and above the collar oxide, and a channel stop formed below the buried-strap junction, wherein a junction between the channel stop and the buried-strap junction is formed in the substrate.

DRAM having improved leakage performance and method for making same

A method for planarizing a dielectric layer on a semiconductor wafer while eliminating a mask and etch step, in accordance with the present invention includes providing a semiconductor wafer having trenches formed in a trench region of a substrate, and forming a dielectric layer on the semiconductor wafer to fill the trenches whereby up features form on flat surfaces of the wafer. An edge portion of the semiconductor wafer is polished to remove a portion of the dielectric layer about the edge portions of the semiconductor wafer. The dielectric layer is polished across the entire semiconductor wafer by employing a single non-stacked polishing pad and a slurry to planarize the trench regions and the up features in a single polish step such that a mask step and etch step for reducing the up features are eliminated from the polishing process.

Planarization process to achieve improved uniformity across semiconductor wafers

A method for rounding corners of a silicon substrate, in accordance with the present invention, includes forming a plateau on a silicon substrate having corners at edges of the plateau. A mask is formed on a top surface of the plateau, which is recessed back from vertical edges of the plateau to provide exposed horizontal portions. Fluorine or Argon dopants are implanted at the corners and on the exposed portions, and the substrate is oxidized such that the corners become rounded providing a gradual transition at the edges of the plateau.

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Mechanicsville, VA, United States of America

Jonathan Philip Davis