Graf Research Corporation

Virginia Tech Intellectual Properties, Inc.

Macaulay-brown, Inc.

Jonathan Peter Graf

Scott Jeffery Harper

Cameron D Patterson

Peter M Athanas

Ali Asgar Ali Akbar Sohanghpurwala

Joshua Nathaniel Edmison

Ali Asgar Sohanghpurwala

Barry L Polakowski

Alan Cook

John K Bowen

Scott Harper

Timothy G Dunham

Steven Frederiksen

Benjamin J Muzal

Carlton Fraley

Mark T Jones

Timothy Dunham

Justin D Rice

Matthew T Shelburne

Jorge A Suris Pletri

Anthony Mahar

Edward Carlisle, Iv

A computer system obtains and/or assists in creation of a natural language description file corresponding to a design, where the design is a hardware design or a software design and processes the natural language description file to extract semantic expressions. One or more intermediate representation data structures is generated from selected ones of the semantic expressions. Each intermediate representation data structure includes natural language design objects, natural language design object properties, and relationships between natural language design objects and/or natural language design object properties. The computer system transforms each intermediate representation data structure into one or more corresponding design verification statements derived from the natural language description file. Those design verification statements are subsequently evaluated against one or more design implementation files corresponding to the design.

Computer-implemented verification of a hardware design implementation against a natural language description of the hardware design or software code against a natural language description of a software application

A computer system traces an original electronic design automation (EDA) implementation process for electronic hardware designs. The original EDA implementation process includes multiple subprocesses to convert a hardware model to a physically-realized electronic circuit. The system inputs a cryptographic key and design information that includes the hardware model, constraints, properties, implementation settings, and other directives for directing the conversion. The cryptographic key and design information are processed to generate a sequence of instructions to execute and provide traceability of each subprocess. For each subprocess, the system gathers intermediate design state and implementation settings resulting from or influencing execution of the subprocess; combines the intermediate design state and implementation settings into a data string and determines a cryptographic hash value for the data string; digitally signs the cryptographic hash value using a digital signature certificate derived from the cryptographic key to generate a signed hash; stores the signed hash and identifiers associated with data files used for determining the cryptographic hash value to an electronic ledger to generate an updated electronic ledger; authenticates the signed hash from the electronic ledger to generate an authenticated signed hash; reconstructs a hash from the data files stored in the electronic ledger to generate a reconstructed hash; compares the authenticated signed hash with the reconstructed hash, and in response to a mismatch, generates an error signal. The steps are repeated for each subsequent subprocess, and the traced EDA implementation process results are stored in memory.

Computer technology to ensure an electronic design automation (EDA) implementation for electronic circuitry is traceable, auditable, and reproducible

An apparatus, method, and system assess the trustworthiness of a design representation while maintaining its confidentiality and thwarting attempts at unauthorized access, misappropriation, and reverse engineering of confidential proprietary aspects of the design representation and/or its bit stream. A utility/tool is provided for trust assessment and verification of designs and/or bit streams. The utility/tool may be instantiated on a semiconductor device or implemented as a utility executable on a mobile computing device or other information processing system, apparatus, or network.

Verification of bitstreams

An apparatus, method and system are disclosed which may be used for assessing the trustworthiness of a particular proprietary microelectronics device design representation in a manner that will maintain its confidentiality and, among other things, thwart attempts at unauthorized access, misappropriation and reverse engineering of the confidential proprietary aspects contained in the design representation and/or its bit stream design implementation format. The disclosed method includes performing a process for assessing/verifying a particular microelectronics device design representation and then providing some indication of the trustworthiness of that representation. An example utility/tool which implements the disclosed method is described that is particularly useful for trust assessment and verification of FPGA designs. The described utility/tool may be instantiated on a semiconductor device or implemented as a software utility executable on a mobile computing device or other information processing system, apparatus or network.

Private verification for FPGA bitstreams

A hardware-facilitated secure software execution environment provides protection of both program instructions and data against unauthorized access and/or execution to maintain confidentiality and integrity of the software or the data during distribution, in external memories, and during execution. The secure computing environment is achieved by using a hardware-based security method and apparatus to provide protection against software privacy and tampering. A Harvard architecture CPU core is instantiated on the same silicon chip along with encryption management unit (EMU) circuitry and secure key management unit (SKU) circuitry. Credential information acquired from one or more sources is combined by the SKU circuitry to generate one or more security keys provided to the EMU for use in decrypting encrypted program instructions and/or data that is obtained from a non-secure, off-chip source such as an external RAM, an information storage device or other network source. In a non-limiting illustrative example implementation, the EMU decrypts a single memory page of encrypted instructions or data per a corresponding encryption key provided by the SKU. Although instantiated on the same chip, the CPU core does not have direct access to the SKU circuitry or to encryption key information generated by the SKU.

Hardware-facilitated secure software execution environment

A method, and system, for reconfiguring an FPGA which has a static region and a dynamic region is provided. The method includes the steps of: (a) providing a dynamic module library having information of predetermined modules; (b) receiving a reconfiguration request external to the FPGA; (c) computing reconfiguration of the FPGA at a predetermined location using predetermined module information from the dynamic module library and the reconfiguration request, and generating reconfigurable partial bitstreams; and (d) sending partial bitstreams from the predetermined location to the FPGA to perform the reconfiguration.

Wires on demand: run-time communication synthesis for reconfigurable computing

Growing community of inventors

Blacksburg, VA, United States of America

Jonathan Peter Graf