Hewlett-packard Development Company, L.p.

Hewlett-packard Company

Jonathan P Lotz

Gregg Bernard Lesartre

Daniel Krueger

Manuel Cabanas-Holmen

Samuel D Naffziger

Donald M Kipp

John T Petersen

Hassan Naser

Russell C Brockmann

Douglas Benson Hunt

Patrick Knebel

John William Bockhaus

Justin Allan Coppin

Steven T Mangelsdorf

Gregory L Ranson

Peter David Maroni

Paul L Perez

Robert E Naas

Thomas N Indermaur

Doug Quarnstrom

Neela Bhakta Gaddis

James Kwok Yue Wai

In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, a voting structure with inputs from the first settable memory element, the second memory element, and control to the settable memory elements determines the logical value held on the third settable memory element. The propagation delay through the third settable memory element is the only propagation delay of the triple redundant latch.

Triple redundant latch design with low delay time

In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, three voting structures with inputs from the first, second, and third settable memory elements and control to the settable memory elements determine the logical values held on the settable memory elements. The propagation delay through a latch is the only propagation delay of the triple redundant latch.

High reliability triple redundant latch with voting logic on each storage node

In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch with integrated testability. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, a voting structure with inputs from the second settable memory element, the third settable memory element and control to the settable memory elements determine the logical value held on the first settable memory element. Data may be scanned into and out of the second settable memory element. Data is propagated through the buffer into the third settable memory element. The third settable memory element may be used to scan data out of the triple redundant latch. The propagation delay through a latch is the only propagation delay of the triple redundant latch.

High reliability triple redundant latch with integrated testability

In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch. Two settable memory elements, and a voting structure/settable memory element set an identical logical value into each settable memory element, and the voting structure/settable memory element. After the settable memory elements, and the voting structure/settable memory element are set, the voting structure/settable memory element with inputs from the first settable memory element, the second memory element, and control to the settable memory elements determines the logical value held on the voting structure/settable memory element. The propagation delay through the voting structure/settable memory element is the only propagation delay of the triple redundant latch.

High reliability memory element with improved delay time

In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch with integrated testability. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, three voting structures with inputs from the first, second, and third settable memory elements, determine the logical value held on each of the settable memory elements. Data may be scanned into and out of the second settable memory element. Data is propagated through the buffer into the third settable memory element. The third settable memory element may be used to scan data out of the triple redundant latch. The propagation delay through a latch is the only propagation delay of the triple redundant latch.

High reliability triple redundant memory element with integrated testability and voting structures on each latch

In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch with storage node recovery. An input driver is connected to the input of three transfer gates. The output of each transfer gate is connected to a separate output of one of three feedback inverters. The transfer gates are controlled by two control inputs. The inputs of the three feedback inverters are connected the output of the forward inverter/majority voter. The output from each of the three feedback inverters are inputs to the forward inverter/majority voter. The output of the forward inverter/majority voter is connected to the input of the output driver. The output of the output driver is the output of the triple redundant latch.

Triple redundant latch design with storage node recovery

The present invention creates a useful BJT by increasing the gain associated with the parasitic BJT on an SOI or bulk type MOSFET. This is done by masking those manufacturing steps that minimize the BJT's beta value, by intentionally increasing the beta value of the BJT, and by driving the base of the BJT with the circuit. Once the gain is increased sufficiently, the BJT may be used productively in the circuit. Because the physical structure of the BJT is already part of the silicon water, its productive use does not require additional space.

Method for creating a useful bipolar junction transistor from a parasitic bipolar junction transistor on a MOSFET

Computer-readable media and methods for designing semiconductor artwork. Basic building blocks, or leaf cells, of an existing piece of semiconductor artwork are transferred to a new piece of semiconductor artwork in order to streamline the design process of the new design. In addition to being transferred, the position of METAL 1 layers within the leaf cells are also analyzed to avert possible design rule violations in the new design.

Hierarchical metal one usage tool for child level leaf cell

In one embodiment, a circuit is provided that includes a precharge device, a DNG FET transistor, and at least one pull-down FET transistor with a floating body. The precharge device is connected to a precharge node for charging it during a precharge state. The DNG FET transistor is connected between a DNG node and a charge sink for operably linking the DNG node to the charge sink during an evaluate state. In addition, the DNG transistor has an associated precharge leakage current. The at least one pull-down FET transistor has an input threshold voltage whose value is inversely affected by its floating body voltage. The at least one pull-down transistor is connected between the precharge node and the DNG node for discharging the precharge node during the evaluate state if so dictated by logical function input values applied to the pull-down transistors during the evaluate state. The DNG leakage current, during the precharge state, draws a sufficient amount of charge from the DNG node to maintain the at least one pull-down transistor body voltage(s) at a sufficiently low value so that the precharge node does not wrongfully evaluate to a discharge level during the evaluate state.

System and method for improving performance of dynamic circuits

Method for creating a useful biopolar junction transistor from a parasitic bipolar junction transistor on a MOSFET

A method of using a fet level simulator to check for races in a digital design. The method comprises varying digital design models input into the simulator. Each model comprises a clock gater circuit producing clocks with differing overlaps and dead times. Raw data files corresponding to each model input are generated by the fet level simulator. The raw data files preferably comprise lists of node values with corresponding time stamps. Corresponding latch node values in the raw data files are compared to identify the nodes of a circuit which are affected by races. Identifying affected latch nodes allows a race's root cause to be quickly pinpointed. Vector inputs to the fet level simulator may be varied. If vector inputs are varied, comparison of the raw data files comprises comparing the files generated for differing models with common vector inputs. Apparatus for implementing the above method is also disclosed. The method and apparatus provide for increased race coverage, and decrease the time and effort required to debug races once their presence is identified.

Method of checking for races in a digital design

User-configurable diagnostic hardware contained on-chip with a microprocessor for the purpose of debugging and monitoring the performance of the microprocessor. Method for using the same. A programmable state machine is coupled to on-chip and off-chip input sources. The state machine may be programmed to look for signal patterns presented by the input sources, and to respond to the occurrence of a defined pattern (or sequence of defined patterns) by driving certain control information onto a state machine output bus. On-chip devices coupled to the output bus take user-definable actions as dictated by the bus. The input sources include user-configurable comparators located within the functional blocks of the microprocessor. The comparators are coupled to storage elements within the microprocessor, and are configured to monitor nodes to determine whether the state of the nodes matches the data contained in the storage elements. By changing data in the storage elements, the programmer may change the information against which the state of the nodes is compared and also the method by which the comparison is made. The output devices include counters. Counter outputs may be used as state machine inputs, so one event may be defined as a function of a different event having occurred a certain number of times. The output devices also include circuitry for generating internal and external triggers. User-configurable multiplexer circuitry may be used to route user-selectable signals from within the microprocessor to the chip's output pads, and to select various internal signals to be used as state machine inputs.

System and method for on-chip debug support and performance monitoring

A system for recovering most recent writer status when a mispredicted branch occurs in a processor that executes instructions out of order. A queue holds instructions stored in the order they are fetched from memory. Each slot in the queue stores a target register that will receive the results of the instruction, and a most recent writer status bit indicating whether the slot is the last instruction to write to the target register. When inserting a new instruction, each slot compares the target register of the new instruction to its target register, and when a match occurs, the slot resets its most recent writer status, and stores the new instruction slot number as a target taker. When a mispredicted branch occurs, the slot compares the mispredicted branch slot to the target taker slot, and when the target taker slot is greater, the slot regains the most recent writer status.

System for storing processor register data after a mispredicted branch

A method for determining intra-bundle dependencies includes a step of pre-inserting target registers of inserting instructions into slots of an instruction queue. The target registers of the inserting instructions are compared to each other and also to the target registers of each instruction in the instruction queue. These comparisons are made to determine which instructions are the most recent writers of the target registers. The method next involves inserting source registers for the inserting instructions and comparing each slot's target register number with these source registers. If a match occurs between a slot's target register and a source register and if that slot furthermore is the most recent writer for that register, then only that slot informs the inserting instruction that the instruction depends upon it for data. The amount of additional hardware in the queue for determining intra-bundle dependencies is minimized since the intra-bundle dependencies are determined with the same set of comparators that determine dependencies between the inserting instructions and the instructions already in the queue.

Growing community of inventors

Fort Collins, CO, United States of America

Jonathan P Lotz