Advanced Micro Devices Corporation

Jonathan P Dowling

Dale E Gulick

Gerald Robert Talbot

Yuan Li

Edoardo Prete

Douglas Elmer Wallace, Jr

Ramon Mangaser

Claude Hilbert

James R Foppiano

Gerald J Merits

Shefali Walia

Manjunath Shivappa

Sharad N Vittal

Wasim I Ullah

Various circuit boards and systems are disclosed. In one aspect a system includes a circuit board and n differential signal via pairs. Each of the n differential signal via pairs has a first signal via and a second signal via and an electrical wall between the first signal via and the second signal via. There is a midline between every two adjacent differential via pairs. There are n ground return path vias. Each of the n ground return path vias is positioned substantially along one of the midlines and not on one of the electrical walls.

Circuit board with return path separated low crosstalk via transition structure

A decision feedback equalization (DFE) receiver and method are provided. The DFE receiver is configured to sample data bits from a data bus. The DFE receiver includes a data sampler configured to sample a current data bit from the data bus using one of a first, second and third voltage reference. The DFE receiver also includes multiplexing logic configured to select one of the first, second and third voltage references based on a prior data bus level. The wherein the first voltage reference is selected if the prior data bus level was a logic zero. The second voltage reference is selected if the prior data bus level was a logic one. The third voltage reference is selected if the prior data bus level was tri-state.

Method and apparatus for using DFE in a system with non-continuous data

A technique for performing signal integrity analysis of a system includes providing a stimulus pattern and a model of the system and performing analog simulation of the model utilizing the stimulus pattern. The stimulus pattern includes sequences of signal transitions with associated transition times and the sequences of signal transitions conform to a bus protocol and the associated transition times are according to characteristics of the system. The stimulus pattern is generated by initializing each of the sequences of signal transitions to an initial signal value and the associated transition times to an initial time, generating subsequent signal values and subsequent transition times by applying protocol rules and calculating timing adjustments for each of a list of transactions; the subsequent signal values and subsequent transition times to be added to the sequences of signal transitions.

Programmable pattern generation for dynamic bus signal integrity analysis

A method and apparatus for impedance matching in systems configured for multiple processors is disclosed. In one embodiment, a computer system includes a first processor socket and a second processor socket, each configured to accommodate a processor. The processor sockets may be electrically coupled to each other. A first I/O node may be electrically coupled to the first processor socket and a second I/O node may be electrically coupled to the second processor socket. A processor may be mounted in the first processor socket, while an impedance matching circuit may be mounted in the second processor socket. The impedance matching circuit may electrically couple the processor mounted in the first processor socket to the second I/O node, thereby allowing the computer system to utilize the I/O capability provided by the second I/O node even when a second processor is not present in the system.

Method and apparatus for impedance matching in systems configured for multiple processors

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Austin, TX, United States of America

Jonathan P Dowling