Intel Corporation

Jonathan P Douglas

J Keith Hodgson

Shahrokh Shahidzadeh

George L Geannopoulos

Kaladhar Radhakrishnan

Alexander Lyakhov

Amit Kumar Jain

David E Duarte

Srikrishnan Venkataraman

Avner Kornfeld

Takao Oshita

James S Ayers

William J Kirby

Scott J Bowden

Anil V Kumar

Gerhard Schrom

Edward Allyn Burton

William J Lambert

Krishna Bharath

Alan Beecher Kyker

Michael J Hill

Dong Zhong

Alexander Slepoy

Sameer Shekhar

James Hadley

Narayanan Natarajan

Daniel J Deleganes

Michael W Rogers

Hector A Aguirre Diaz

Fabrice Paillet

Ankush Varma

Nasser A Kurd

Kevin X Zhang

Gregory F Taylor

Anant S Deval

Julien Sebot

Chin Lee Kuan

Praveen Mosalikanti

Daniel J Ragland

Zhanping Chen

William Dawson Kesling

Rinkle Jain

Samie B Samaan

Dawson Kesling

Narayanan Raghuraman

John Fallin

Chiu Keung Tang

Ravi Sankar Vunnam

Derek B Feltham

Tim Gates

Ray Ramadorai

James Steven Fintel

Tim Abels

Vivek Saxena

Mauricio Aguilar Salas

Sreedhar Narayanaswamy

Shivadarshan Rajeurs

Chih-Chung Jonathan Wei

Techniques and mechanisms for determining an operational mode of a voltage regulator. In an embodiment, an integrated circuit (IC) die is coupled to receive power from a voltage regulator (VR) via a power delivery network (PDN) which comprises circuitry in or on a substrate, such as that of a printed circuit board. The IC die receives from the substrate information indicating a characteristic of a parasitic impedance at the substrate. Based on the information, a controller unit at the IC die selects one of multiple VR modes which each correspond to a respective one of different parasitic impedance characteristics. The controller then signals the VR to provide the selected mode. In an embodiment one of the VR modes corresponds to a relatively high impedance, and also corresponds to a relatively stable sensitivity function in a frequency range above a control bandwidth.

Device, method and system to determine a mode of voltage regulation based on parasitics of a power delivery network

An apparatus and method is described that digitally coordinates dynamically adaptable clock and voltage supply to significantly reduce the energy consumed by a processor without impacting its performance or latency. A signal is generated that indicates a long latency operation. This signal is used to reduce power supply voltage and frequency of the adaptable clock. An early resume indicator is generated a few nanoseconds before normal operations are about to resume. This early resume signal is used to power up the power-downed voltage regulator, and/or can increase frequency and/or supply voltage back to normal level before normal processor operations are about to resume.

Digitally coordinated dynamically adaptable clock and voltage supply apparatus and method

Embodiments disclosed herein include electronics packages with improved thermal pathways. In an embodiment, an electronics package includes a package substrate. In an embodiment, the package substrate comprises a plurality of backside layers, a plurality of front-side layers, and a core layer between the plurality of backside layers and the plurality of front-side layers. In an embodiment, an inductor is embedded in the plurality of backside layers. In an embodiment, a plurality of bumps are formed over the front-side layers and thermally coupled to the inductor. In an embodiment, the plurality of bumps are thermally coupled to the core layer by a plurality of vias.

Structures to facilitate heat transfer within package layers to thermal heat sink and motherboard

Disclosed is an N:1 (where N is an integer such as 3 or higher) resonant star topology converter to generate an input supply (e.g., 1.8V) for a processor (e.g., a system-on-chip (SOC)) from a higher power supply source (e.g., 12.6V) such as a battery or other source. The resonant star topology based regulator can be realized by a combination of on-die and on-package components as opposed to voltage regulators on motherboard with discrete inductor and capacitors. In one example, capacitors of the N:1 resonant star topology are implemented as multilayer ceramic capacitors (MLCC). The architecture of the N:1 resonant star topology based regulator results in high bandwidth. For example, compared to traditional step-down voltage regulators, the N:1 resonant star topology based regulator exhibits ten times higher bandwidth.

On-package high-bandwidth resonant switched capacitor voltage regulator

Circuitry to apply heat to a die while the die junction temperature is below a minimum die junction temperature of an operating die junction temperature range for the die is provided. The circuitry to avoid a system boot failure when the die junction temperature is below the operating die junction temperature range of the die.

Method and apparatus to control temperature of a semiconductor die in a computer system

Techniques and mechanisms for mitigating an overshoot of a supply voltage provided with a voltage regulator (VR). In an embodiment, buck converter functionality of a VR is provided with first circuitry comprising a first inductor and first switch circuits variously coupled thereto. Second circuitry of the VR comprises a second inductor and second switch circuits variously coupled thereto. In response to an indication of a voltage overshoot condition, respective states of the first switch circuits and the second switch circuits are configured to enable a conductive path for dissipating energy with the first inductor, the second inductor, and various ones of the first switch circuits and the second switch circuits. In another embodiment, mitigating the voltage overshoot condition comprises alternately toggling between two different configurations of the second switch circuits.

Device, method and system to mitigate a voltage overshoot event

Described is an apparatus which comprises: a first voltage regulator (VR) coupled to first one or more inductors, the first VR is to provide power to a first power domain; and a second VR coupled to second one or more inductors at least one of which is inductively coupled to at least one of the first one or more inductors, the second VR is to provide power to a second power domain separate from the first power domain, wherein there is a non-zero phase angle offset between switching transistors of the first VR relative to the second VR.

Apparatus and method to reduce power losses in an integrated voltage regulator

Some embodiments include apparatuses and methods of using such apparatuses. One of the apparatuses includes voltage regulators in an integrated circuit device, and a frequency control block and a module included in the integrated circuit device. Each of the voltage regulators includes a current sensor. The frequency control block operates to provide a clock signal to each of the voltage regulators. The clock signal has a frequency based on digital information. The module operates to receive a current from the current sensor of each of the voltage regulators and provides the digital information to the frequency control block to control the frequency of the clock signal. The digital information has a value based on the current from each of the current sensors.

Voltage regulator circuitry including module for switching frequency self-optimization

Described is an analog to digital converter (ADC) which comprises: a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to perform chopping to cancel common-mode noise; and one or more counters coupled to the sigma-delta modulator to generate a digital code representative of the analog signal.

Low power analog to digital converter

Described is an apparatus having a non-linear control to manage power supply droop at an output of a voltage regulator. The apparatus comprises: a first inductor for coupling to a load; a capacitor, coupled to the first inductor, and for coupling to the load; a first high-side switch couple to the first inductor; a first low-side switch coupled to the first inductor; a bridge controller to control when to turn on and off the first high-side and first low-side switches; and a non-linear control (NLC) unit to monitor output voltage on the load, and to cause the bridge controller to turn on the first high-side switch and turn off the first low-side switch when a voltage droop is detected on the load.

Non-linear control for voltage regulator

Described is an apparatus for providing spread-spectrum to a clock signal. The apparatus comprises: an oscillator to generate an output clock signal, the oscillator to receive an adjustable reference signal to adjust frequency of the output clock signal; a first circuit to provide a first signal indicative of a center frequency of the output clock signal; a second circuit to generate a switching waveform to provide spread-spectrum for the output clock signal; and a third circuit, coupled to the first and second circuits, to provide the adjustable reference signal according to the first signal and the switching waveform.

Spread-spectrum apparatus for voltage regulator

In one embodiment, the present invention includes a method for determining if a system is compatible with an upgrade to a hardware resource of the system, receiving instructions from a remote server to upgrade the hardware resource if the system is compatible, and programming the hardware resource based on the instructions. In one such embodiment, the hardware resource may be programmed via programmable fuses to enable circuitry of the hardware resource. Other embodiments are described and claimed.

In-system reconfiguring of hardware resources

Growing community of inventors

Olympia, WA, United States of America

Jonathan P Douglas