Advanced Micro Devices Corporation

Other

Ati Technologies Ulc

Alpha Processor, Inc.

Globalfoundries Inc.

Api Networks, Inc.

Jonathan Mercer Owen

Mark Douglas Hummel

Maurice B Steinman

James B Keller

Derrick R Meyer

John Kalamatianos

Alexander J Branover

Guhan Krishnan

Paul Mackey

Larry David Hewitt

Michael J Osborn

Paul C Miranda

Antonio Asaro

Norman M Hack

Ralf Flemming

Joerg Winkler

Thomas Kunjan

Don Cherepacha

Brian W Amick

Denis J Foley

Frank P Helms

Hanwoo Cho

William Kurt Lewchuk

Denis Rystsov

Carl D Dietz

Sean T White

Douglas Richard Beard

Sajosh Janarthanam

Alex Branover

Arthur A Sherman

Kurt Lewchuk

Thomas R Kunjan

William K Lewchuk

A method and apparatus for training read latency of a memory are disclosed. A memory controller includes a command FIFO configured to convey commands to a memory, a data queue coupled to receive data from the memory, and a register configured to provide a value indicative of a number of cycles of a first clock signal after which data is valid. During a startup routine, the memory controller is configured to compare data received by the data queue to a known data pattern after a specified number of cycles of the first clock signal have elapsed. The memory controller is further to configured to decrement the first value and repeat conveying and comparing if the data received matches the data pattern. If the received data does not match the data pattern for any attempted read of the memory, the memory controller is configured to program a second value into the register.

Method and apparatus to reduce memory read latency

A method and apparatus for dynamically controlling a cache size is disclosed. In one embodiment, a method includes changing an operating point of a processor from a first operating point to a second operating point, and selectively removing power from one or more ways of a cache memory responsive to changing the operating point. The method further includes processing one or more instructions in the processor subsequent to removing power from the one or more ways of the cache memory, wherein said processing includes accessing one or more ways of the cache memory from which power was not removed.

Method and apparatus for cache control

A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is based on an indicator of a previous memory request selected for placement in the merged memory request stream.

Hierarchical memory arbitration technique for disparate sources

A system and method for data allocation in a shared cache memory of a computing system are contemplated. Each cache way of a shared set-associative cache is accessible to multiple sources, such as one or more processor cores, a graphics processing unit (GPU), an input/output (I/O) device, or multiple different software threads. A shared cache controller enables or disables access separately to each of the cache ways based upon the corresponding source of a received memory request. One or more configuration and status registers (CSRs) store encoded values used to alter accessibility to each of the shared cache ways. The control of the accessibility of the shared cache ways via altering stored values in the CSRs may be used to create a pseudo-RAM structure within the shared cache and to progressively reduce the size of the shared cache during a power-down sequence while the shared cache continues operation.

Method for way allocation and way locking in a cache

A first in, first out (FIFO) queue includes logic to provide detection of operational errors in the FIFO queue. The FIFO queue includes entries to store data written to the FIFO queue and signature bits, each signature bit corresponding to one of the entries. A test pattern and a read signature register includes a number of bits greater than a depth of the FIFO queue. A comparator compares the test pattern to the read signature register and output an error signal indicating whether the test pattern matches the read signature register.

Error detection in FIFO queues using signature bits

A method for transitioning power states in a device includes designating a first reduced power state as a target power state. A first expected residency for the target power state is determined based on a counting of activity requests associated with the device. The device is transitioned to the target power state responsive to the expected residency satisfying a first predetermined threshold.

Method and apparatus for transitioning devices between power states based on activity request frequency

A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is at least partially based on an indicator of a previous memory request selected for placement in the merged memory request stream.

A method of receiving communications at a data processing device includes receiving a packet from a virtual channel associated with a physical communication link. The packet is associated with a link virtual channel, and is stored in a storage location with the link virtual channel. Multiple internal virtual channels can be associated with the link virtual channel. A pointer to the storage location is enqueued in one of a plurality of FIFOs associated with one of the internal virtual channels. Each FIFO of the plurality of FIFOs stores pointers associated with a different internal virtual channel, allowing receiver arbitration logic to reorder between internal virtual channels based on internal resource availability and current priorities among virtual channels. This reduces the likelihood of communication deadlock and supports multiple classes of service.

Data processing device interface and methods thereof

A data transfer device transfers data between two clock domains of a data processing device when the data processing device is in a test mode. The data transfer device receives clock signals associated with each clock domain. To transfer data from a first clock domain to a second clock domain the data transfer device identifies transitions of clock signals associated with each clock domain that are sufficiently remote from each other so that data can deterministically be provided by one clock domain and sampled by the other. This ensures that data can be transferred between the clock domains deterministically even when the phase relationship between the clock signals is indeterminate.

Data transfer device and method thereof

A processor can operate in different power modes. In an active power mode, the processor executes software. In response to receiving a halt indication from the software, hardware at the processor evaluates bus transactions for the processor. If the bus transactions meet a heuristic, hardware places a processor core in a lower power mode, such as a retention mode. Because the bus transactions are evaluated by hardware, rather than by software, and the software is not required to perform handshakes and other protocols to place the processor in the lower power mode, the processor is able to place the processor core into the lower power mode more quickly, thereby conserving power.

Dynamic processor power management device and method thereof

A method of controlling memory read behavior in PCI devices includes connecting a master PCI device to a PCI bus. The master PCI device is constructed and arranged to issue a Memory Read Line or a Memory Read Multiple initial command. A target PCI bridge device is connected to the PCI bus. The target PCI bridge device is constructed and arranged to prefetch data from host memory on behalf of the master PCI device and to store the prefetched data. A data transfer transaction is established between the master PCI device and the target PCI bridge device and prefetched data is stored at the target PCI bridge device. A bit is selectively preset in at least one of the PCI devices such that if a disconnect of the transaction occurs, the target PCI bridge device recognizes a subsequent request as a continuation of the initial request and sends prefetched data to the master PCI device.

Control of PCI memory read behavior using memory read alias and memory command reissue bits

A messaging scheme to synchronize processes within a distributed memory multiprocessing computer system having two or more processing nodes interconnected using an interconnect structure of dual-unidirectional links. Each unidirectional link forms a point-to-point interconnect to transfer packetized information between two processing nodes. A lock acquisition request from a lock requesting node is placed into service by an arbitrating node when no previous lock requests are pending for service. The arbitrating node transmits a broadcast message to all nodes in the system, which, in turn, respond with a corresponding probe response message to inform the arbitrating node of cessation of issuance of new requests by the node sending the probe response message. The arbitrating node informs the lock requesting node of the requesting node's lock ownership by transmitting a target done message thereto. After completion of lock operations, the lock requesting node sends a lock release request to the arbitrating node, which, in turn, informs all processing nodes of lock release by transmitting another broadcast message within the system. The messaging protocol is completed when each node sends another probe response to the arbitrating node, which, in turn, sends a final target done message to the lock requesting node. Lock operations are performed without contention for system resources and without deadlocks among various processing nodes.

Implementing locks in a distributed processing system

A first portion of a communication link is operated in a power savings mode at the same time that a second portion of the communication link is operated in a normal operational mode. For the first portion, a refresh mode is entered from the power savings mode in which one or more training patterns are transmitted over the first portion, while the second portion remains in the normal operational mode. An indication when to activate and deactivate the refresh mode may be sent over the second portion of the communication link. The refresh mode may be periodically entered from the power savings mode based on an interval register specifying the amount of time the communication link should remain in the power savings mode before a refresh occurs. In addition, the amount of time spent in the refresh mode may be programmable.

In-band power management in a communication link

A computer system includes a first and a second integrated circuit coupled by a communication link. The communication link operates in a power savings mode in which data is not transmitted over the link. Periodically, the communication link enters a training phase in which training patterns are transmitted over the communication link for a predetermined time period. The communication link returns to the power savings mode after the predetermined time period has elapsed. At least one sideband signal, separate from the communication link, and coupled between the first and second integrated circuits, is used to indicate when to enter the training phase from the power savings mode and exit the training phase and return to the power savings mode.

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Northborough, MA, United States of America

Jonathan Mercer Owen