Cisco Technology, Inc.

Cisco Systems Inc.

Jonathan M Parlan

Robert Hoffman

Li Li

Fabio Rodolfo Maino

Raymond Kloth

Shashi Kumar

Jie Xue

Xinli Gu

Pawan Agrawal

Nandakumar Krishnan

Calvin C Wong

Ying Huang

Raymond J Kloth

Methods and apparatus for performing encryption for data at rest at a port of a network device such as a switch are disclosed. Specifically, when data is received from a host during a write to a storage medium such as a disk, the data is encrypted by the port prior to transmitting the encrypted data to the storage medium. Similarly, when a host attempts to read data from the storage medium, the port of the network device receives the encrypted data from the storage medium, decrypts the data, and transmits the decrypted data to the host. In this manner, encryption and decryption of data at rest are supported by the port of the network device.

Method and apparatus for performing encryption of data at rest at a port of a network device

In one embodiment, the reliability of the L2 power and/or ground sub-arrays of contacts of a functional integrated circuit device is verified by applying a reference voltage to a selected contact in sub-array and sequentially measuring the voltage at other contacts in the sub-array. If the voltage levels are greater than a threshold voltage level then the functional integrated circuit device is verified as being reliable.

Monitoring of interconnect reliability using a programmable device

Methods and apparatus are disclosed for generating and checking CRC values using a multi-byte CRC generator and a binary Galois field (&ldquo;GF2&rdquo;) multiplier. These methods and apparatus could be used in an unlimited number of applications and environments, such as part of computer or communications device (e.g., router or switch). The CRC generator and/or checker may be implemented singularly or in a combination of technologies, including, but not limited to, software, firmware, hardware, customized circuitry, application-specific integrated circuits, etc. A CRC generator is used to calculate a preliminary CRC value on a block of information. This CRC generator may be a balanced XOR tree or some other implementation, which calculates the preliminary CRC value on groups of n bytes of data at a time, where n is some integer greater than one. For example, when data is transferred over a 512 wide bit bus, typically the value of n would be 64 (i.e., 512 bits divided by 8 bits per byte). Because the number of bytes in the data group may not be an even multiple of the value of n, one or more bytes of value zero may be appended to the data group to make it an even multiple, with the preliminary CRC being calculated on the entire appended data group. A GF2 multiplier uses the preliminary CRC value and the number of appended bytes of value zero to calculate the actual CRC value of the information.

Method and apparatus for generating and checking cyclic redundancy code (CRC) values using a CRC generator and binary galois field multiplier

A method of managing free entries in a CAM using virtual page pre-fetch is defined. The memory locations in a CAM are partitioned into multiple virtual pages (VP). The allocation of memory location to VPs is independent of the physical address of the location. The address of an empty location (free entry) from each VP is pre-fetched and is maintained in a free entry list. Consecutive write operations are scheduled in different VPs to avoid a back-to-back write in the same VP which eliminates resource contention. When data is retrieved from a location in the CAM, that location becomes available for next write. Because the allocation of a location to VPs is independent of the physical address of the location, when the location becomes available, a new VP assignment is made for that location.

Automated free entry management for content-addressable memory using virtual page pre-fetch

A special memory overlay circuit uses a first DRAM buffer memory in combination with a second faster SRAM buffer memory to reduce the time required to translate information into different network protocols. Packet data is stored in the DRAM buffer memory and packet headers requiring manipulation are stored in the SRAM buffer memory. Because the SRAM has a faster data access time than the DRAM buffer memory, a processor can reformat the packet header into different network protocols in a shorter amount of time. Packet headers also use a relatively small amount of memory compared to remaining packet data. Since the SRAM buffer memory is only used for storing packet headers, relatively little additional cost is required to utilize the faster SRAM memory while substantially increasing network performance.

Internetworking device with enhanced protocol translation circuit

Growing community of inventors

Los Altos, CA, United States of America

Jonathan M Parlan