International Business Machines Corporation

Jonathan M McKenna

Wagdi William Abadeer

William R Tonti

Robert J Gauthier, Jr

Jed Hickory Rankin

Jeffrey Scott Brown

Eric Adler

Edward W Sengle

Wayne Frederick Ellis

Patrick R Hansen

A method for detecting semiconductor process stress-induced defects. The method comprising: providing a polysilicon-bounded test diode, the diode comprising a diffused first region within an upper portion of a second region of a silicon substrate, the second region of an opposite dopant type from the first region, the first region surrounded by a peripheral dielectric isolation, a peripheral polysilicon gate comprising a polysilicon layer over a dielectric layer and the gate overlapping a peripheral portion of the first region; stressing the diode; and monitoring the stressed diode for spikes in gate current during the stress, determining the frequency distribution of the slope of the forward bias voltage versus the first region current at the pre-selected forward bias voltage and monitoring, after stress, the diode for soft breakdown. A DRAM cell may be substituted for the diode. The use of the diode as an antifuse is also disclosed.

Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure

A ring oscillator (and test circuit incorporating the ring oscillator and test method therefor) includes an odd number of elements interconnected in a serially-connected infinite loop, each oscillator element having an associated programmable delay feature. The circuit can be used to measure effects of Negative Bias Temperature Instability (NBTI) in p-channel MOSFETs (PFETs).

System and method for measuring circuit performance degradation due to PFET negative bias temperature instability (NBTI)

A method for detecting semiconductor process stress-induced defects. The method comprising: providing a polysilicon-bounded test diode, the diode comprising a diffused first region within an upper portion of a second region of a silicon substrate, the second region of an opposite dopant type from the first region, the first region surrounded by a peripheral dielectric isolation, a peripheral polysilicon gate comprising a polysilicon layer over a dielectric layer and the gate overlapping a peripheral portion of the first region; stressing the diode; and monitoring the stressed diode for spikes in gate current during the stress, determining the frequency distribution of the slope of the forward bias voltage versus the first region current at the pre-selected forward bias voltage and monitoring, after stress, the diode for soft breakdown. A DRAM cell may,be substituted for the diode. The use of the diode as an antifuse is also disclosed.

A method of determining time-to-breakdown of a gate dielectric in an NFET or a PFET transistor. For an NFET transistor, the method includes providing an N&plus; injector ring in the p-substrate and forward biasing the N&plus; injector ring with respect to the p-substrate. A first positive reference voltage level is applied to the source and the drain regions. A second positive reference voltage level is applied to the gate dielectric. The first and second positive reference voltage levels are maintained on the transistor until breakdown of the gate dielectric occurs. Another embodiment of the method may be used in a PFET transistor.

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Ann Arbor, MI, United States of America

Jonathan M McKenna