Sk Hynix Nand Product Solutions Corp.

Intel Corporation

Jonathan M Hughes

Sanjeev N Trika

Piotr Wysocki

Jackson Ellis

Ziye Yang

Gang Cao

Xiaodong Liu

Changpeng Liu

James R Harris

Benjamin Walker

Qihua Dai

Gregory Tucker

Anand S Ramalingam

Adrian R Pearson

David R Noeldner

Michael Mesnier

Kapil Karkra

David B Carlton

Gamil A Cain

Neelesh Vemula

Thomas R Bowen

Gregory B Tucker

Jonathan De Vries

Brennan A Watt

Dimpesh Patel

Robert E Frickey

Teddy Gordon Greer

Darshan Mallapur Vishwanath

Timothy Hallett

Anilmurali Bhaviri

Muhammad Mohsin Awan

Teddy Greer

Niels Juel Reimers

Emily Po-Kay Chung

Kailaash Rajagopalan

Mahesh Govindane

John Nolan

Bindu Madhavi Khambam

Matthew Fitzpatrick

Sam Povilus

A device and related method, the device including a port, memory circuitry, and processing circuitry which is coupled to the port and to the memory circuitry. The processing circuitry receives multiple commands through the port, wherein the multiple commands are from at least two hosts using an interposer and wherein each command of the multiple commands includes a respective memory address and a respective port identification (ID). The processing circuitry segments each of the received commands into multiple segments, each segment being of a predetermined transfer size. The processing circuitry also transmits each segment of each command to a respective data structure instantiation corresponding to the port ID of the respective received command and performs data transfer for each segment of the multiple segments by accessing the memory circuitry at each respective memory address associated with each segment.

Devices and methods for deterministic interleaving of data from multiple hosts connected to a single port

A device and related method, the device including system memory for storing at least two queue groups, each of which includes commands, and processing circuitry. For each respective queue group, the processing circuitry determines an allocated command value indicative of a number of commands that are capable of being fetched from the respective queue group, determines a number of outstanding commands to be fetched from the respective queue group, and compares the allocated command value to the number of outstanding commands to be fetched for the respective queue group. When the allocated command value is greater than the number of outstanding commands to be fetched for the respective queue group, the processing circuitry designates the respective queue group as an available queue group. The processing circuitry then selects a queue group from the designated available queue groups and fetches at least one command from the selected queue group.

Devices and methods for managing command fetch and command execution

Systems and methods for a controller including controller memory and logic are presented herein. The logic is configured to control access to a persistent storage media and, in response to one or more commands, determine an intermediate parity value based on a first parity calculation by sending a uni-directional command to the persistent storage media. The logic is further configured to store, in the controller memory, the intermediate parity value, and determine a final parity value based on the intermediate parity value and a second parity calculation.

ON-SSD erasure coding with uni-directional commands

A device and related method, the device including memory and processing circuitry. The memory includes sets of source memory bands and a defragmentation destination memory band. Each set of source memory bands includes source memory bands and at least one portion of each source memory band stores valid data. The processing circuitry determines a merit score corresponding to each source memory band based on one or more characteristics of portions of data of each corresponding source memory band and determines, for each set of source memory bands, a respective source memory band that corresponds to a second-highest merit score. The processing circuitry identifies a set of source memory bands that includes a source memory band corresponding to a highest second-highest merit score and stores at least one portion of valid data from the source memory bands of the identified set of source memory bands to the defragmentation destination memory band.

Devices and methods for improving multi-stream write amplification factor

An embodiment of an electronic storage system includes one or more storage drives, at least one or more of the storage drives supporting erasure coding (EC); and a controller including logic to control local access to the one or more storage drives. The controller, in response to a write command, is to for one or more storage drives, allocate an intermediate buffer in the storage drive's non-volatile memory (NVM) to store intermediate data. The controller is to issue commands to a first storage drive to read old data, compute the intermediate data of the first storage drive as XOR of the old data and new data received in the write command, and atomically write the intermediate data of the first storage drive to the intermediate buffer of the first storage drive and write the new data to the first storage drive's NVM. The controller is to read the intermediate data of the first storage drive from the intermediate buffer of the first storage drive. The controller is further to issue commands to one or more EC storage drives to read the old data, compute result data as the old data XOR a galois field coefficient of the one or more EC storage drives multiplied by the intermediate data, and atomically write the old data to the intermediate buffer of the one or more EC storage drives and write the result data to the one or more EC storage drive's NVM. Other embodiments are disclosed and claimed.

Erasure coding write hole closure for solid-state drive (SSD) erasure coding

A system and related method, including a first processor core, a second processor core and a control circuitry to receive requests to update existing firmware of the first processor core to a new firmware. The control circuitry loads existing firmware onto the second processor core and migrates data associated with the existing firmware on the first processor core to the second processor core. The control circuitry stops the transaction execution by the first processor core while causing the second processor core to execute transactions in place of the first processor core. The control circuitry restarts the first processor core, replaces the existing firmware on the first processor core with the new firmware, and migrates data of the existing firmware on the second processor core to the first processor core. The control circuitry stops the transaction execution of the second processor core and causes the first processor core to execute transactions.

Methods and systems for updating device firmware while maintaining state and connectivity

Systems and methods for a controller including controller memory and logic are presented herein. The logic is configured to control access to a persistent storage media and, in response to one or more commands, the logic determines an intermediate parity value based on a first parity calculation, and using the intermediate parity value determines a final parity value based on the intermediate parity value and a second parity calculation. Determining the intermediate parity value includes sending a uni-directional command to read an old data value from an address indicated in the uni-directional command, perform an exclusive-or operation on the old data value and a new data value indicated in the uni-directional command to determine the intermediate parity value and store, in the persistent storage media, the intermediate parity value at a location associated to an index indicated in the uni-directional command.

On-SSD erasure coding with uni-directional commands

A self-encrypting drive (SED) comprises an SED controller and a nonvolatile storage medium (NVSM) responsive to the SED controller. The SED controller enables the SED to perform operations comprising: (a) receiving an encrypted media encryption key (eMEK) for a client; (b) decrypting the eMEK into an unencrypted media encryption key (MEK); (c) receiving a write request from the client, wherein the write request includes data to be stored and a key tag value associated with the MEK; (d) using the key tag value to select the MEK for the write request; (e) using the MEK for the write request to encrypt the data from the client; and (f) storing the encrypted data in a region of the NVSM allocated to the client. Other embodiments are described and claimed.

Technology for fine-grain encryption and secure key injection on self-encrypting drives

An embodiment of a semiconductor apparatus may include technology to selectively determine a set of data for background refresh based at least in part on host-provided information, and refresh the determined set of data on a persistent storage media as a background operation. Other embodiments are disclosed and claimed.

Selective background data refresh for SSDs

A method and system to improve the performance of a multi-level cell (MLC) NAND flash memory. In one embodiment of the invention, the metadata associated with the data stored in a MLC NAND flash memory is stored only in one or more lower pages of the MLC NAND flash memory. The MLC NAND flash memory has lower and upper pages, where the lower pages have a faster programming time or rate than the upper pages in one embodiment of the invention. By storing the metadata only in the pages of the MLC NAND flash memory that have low latencies of programming, the quality of service (QoS) of the MLC NAND flash memory can be improved.

Method and system to improve the performance of a multi-level cell (MLC) NAND flash memory

Growing community of inventors

Longmont, CO, United States of America

Jonathan M Hughes