Apple Inc.

3com Corporation

Siemens Medical Systems, Inc.

Jonathan M Fitch

Ronald Ray Hochsprung

Carl C Hewitt

Clifford Mark Kelly

William A Scott

Eric C Hewitt

Alan J Luckow

John A Bryant

James S Gable

Ben Robert Manuto

Marc Auerbach

An automated method for periodically evaluating media streams on a network of computers. The invention is used to determine the availability of various media streams and identify various characteristics of each stream. By repeatedly obtaining the addresses, attempting to establish communication with each media stream, and then reporting the results the system can verify that each media stream is accessible and report various characteristics of the stream.

Search engine to verify streaming audio sources

A sampling system includes an input terminal for receiving a data signal having a signal component and possibly a noise component. A sampler samples the data signal at a sample rate set in responsive to a control signal. A noise detector detects the presence of a noise component, and if a noise component is detected, generates the control signal conditioning the sampler to sample the data signal at a first sample rate satisfying the Nyquist criterion for the data signal including the noise component, and otherwise generating the control signal conditioning the sampler to sample the data signal at a second data rate satisfying the Nyquist criterion for the data signal including only the signal component.

System for sampling a data signal

Radio

An address selective address mapping system comprises an address translation circuit, a central processing unit (CPU), a data cache, and a memory. The address outputs of the CPU are coupled to a first address bus, while the address inputs of the data cache and memory are coupled to a second address bus. The address translation circuit's inputs are coupled to the first address bus, and the address translation circuit's outputs are coupled to the second address bus. The CPU sends a pointer address via the first address bus to the address translation circuit. The address translation circuit determines whether the pointer address indicates that the next source instruction is within the subset of the most frequently executed source instructions. If so, the address translation circuit maps the pointer address to an address within the data cache. If not, the pointer address is routed through the address translation circuit unchanged. The pointer address is next routed to the data cache and to the RAM via the second address bus. If the pointer address was mapped to a data cache address, the data cache outputs the pointer to the next emulation routine on the data bus. If the pointer address was not mapped to a data cache address, the pointer to the next emulation routine is output to the data bus at the data outputs of the memory. The present invention also includes a method for manufacturing an address selective address mapping system.

Address selective emulation routine pointer address mapping system

An apparatus and method for emulation routine pointer prefetch are disclosed. The apparatus includes an emulated program counter (EPC), a prefetch state machine, a summing device, an opcode storage device, and a pointer storage device. The EPC, opcode storage device and pointer storage device are coupled to a bus to receive, store and output an emulated program counter value, an opcode value and a pointer to a next emulation routine. The EPC, opcode storage device, and pointer storage device are controlled by the prefetch state machine, which also is coupled to the bus to detect a reference to a reserved memory address and stores an updated emulated program counter value in the EPC using the summing device. The prefetch state machine uses the EPC value to prefetch the next source instruction to be emulated in a first memory operation. A portion of the prefetched source instruction is the opcode value and is stored in the opcode storage device. The prefetch state machine uses the opcode value in a second memory operation to retrieve a pointer to a corresponding emulation routine which is stored in the pointer storage device. The method for emulation routine pointer prefetch preferably comprises the steps of determining if a currently executing emulation routine has issued an instruction to update the EPC; prefetching a next source instruction based upon the value of the EPC; and using an opcode within the prefetched source instruction to prefetch a pointer to a next emulation routine corresponding to the prefetched source instruction.

Apparatus and method for emulation routine pointer prefetch

A memory architecture including a memory cache which uses a single level of write buffering in combination with page mode writes to attain zero wait state operation for most memory accesses by a microprocessor. By the use of such a memory architecture, the speed advantages of more expensive buffering schemes, such as FIFO buffering, are obtained using less complex designs. The memory architecture utilizes same page detection logic and latching circuitry and takes advantage of a feature built into industry standard dynamic RAMs, namely page mode writes, to perform writes to memory which allow the processor to be freed before the write is completed for the most frequently occurring type of write operations.

Memory architecture using page mode writes and single level write

An apparatus for emulation routine control transfer creates a jump host instruction (JHI) containing the address of a next emulation routine during the execution of a current emulation routine and outputs the JHI at the end of current emulation routine for transfer of host processor control. The apparatus preferably comprises: an emulated program counter (EPC), a summing means, a state machine, a pointer storage means, an opcode storage means, and a jump instruction circuit. The state machine is preferably coupled to control the loading of the EPC, the loading of the opcode storage means, the summing means, the pointer storage means and the operation of the jump instruction circuit. The pointer storage means is preferably coupled between the data bus and the jump instruction circuit. The state machine preferably issues commands on the control bus and directly to the summing means and the jump instruction circuit to prefetch the next emulation routine, create a jump instruction to the beginning of the next emulation routine and assert the jump instruction on the bus at the appropriate time to transfer directly from one emulation routine to the next using the single host jump instruction. The jump host instruction is placed upon the host processor's instruction bus after execution of the final instruction within a current emulation routine. Thus, the execution of the next emulation routine begins immediately after the execution of the jump host instruction, and significant amounts of processing time associated with the dispatch loop are eliminated.

Apparatus and method for emulation routine control transfer via host

An instruction mapping system comprises an instruction mapping circuit, a central processing unit (CPU), a data cache, and a memory. The address outputs of the CPU are coupled to a first address bus, while the address inputs of the data cache and memory are coupled to a second address bus. The instruction mapping circuit's address inputs are coupled to the first address bus, and the instruction mapping circuit's outputs are coupled to the second address bus. The CPU sends a pointer address via the first address bus to the instruction mapping circuit. The instruction mapping circuit determines whether the pointer address indicates that the next source instruction is within the subset of most frequently executed source instructions. If so, the instruction mapping circuit maps the pointer address to an address within the data cache. If not, the pointer address is routed through the instruction mapping circuit unchanged. The pointer address is next routed to the data cache and to the RAM via the second address bus. If the pointer address was mapped to a data cache address, the data cache outputs the pointer to the next emulation routine on the data bus. If the pointer address was not mapped to a data cache address, the pointer to the next emulation routine is output on the data bus at the data outputs of the memory. The present invention also includes a method for manufacturing an instruction mapping system.

An apparatus for emulation routine instruction issue comprises a bus signal router, a state machine, a virtual program counter (VPC) circuit, an emulated program counter (EPC), a summing circuit, an opcode storage register, and a pointer storage register. The VPC circuit maintains the VPC value under the direction of the state machine. In response to a next instruction request issued by the central processing unit (CPU), the state machine outputs the VPC to an instruction address bus, transferring the host instruction stored at the address indicated by the VPC to the instruction bus for issue to the CPU. After a next host instruction request, the state machine updates the VPC value. Concurrent with the execution of the current emulation routine, the state machine prefetches the nest emulation routine pointer (NERP) by issuing DMA commands and commands to the EPC, the opcode storage means, and the pointer storage means. If the final host instruction in the current emulation routine has been reached, the state machine assigns the NERP to the VPC and outputs the VPC to the instruction address bus. A method for Emulation Routine Instruction Issue comprises the steps of determining if a next host instruction request has been made by the CPU; outputting the VPC to the instruction address bus; and updating the VPC; and prefetching the NERP concurrent with the execution of the host instructions in the current emulation routine.

Apparatus and method for emulation routine instruction issue

A memory system where a cache miss is fielded with a retry access to main memory, but instead of waiting for the microprocessor to resynchronize and re-initiate the memory cycle, the memory cycle is started immediately. The speed of the tag array is specified so that the status of the cache, hit or miss, is known at the same time that the microprocessor's memory cycle start signal is known to be valid. The addresses are then latched and the memory cycle is started in anticipation of the retried cycle. The access time of memory is then overlapped with microprocessor resynchronization and memory cycle reinitialization. By using this technique, clock cycles are needed for the initial cycle, additional clock cycles are needed to perform the resynchronization, and additional clock cycles are needed for the retried cycle since the data is already waiting from memory. The above-described improvement is implemented by decoupling the direct connection of the memory array from the address bus. Additionally, a state machine modifies the operation of the memory controller so that the access time of the memory is overlapped with microprocessor resynchronization and memory cycle reinitialization.

Cache memory systems that accesses main memory without wait states

A circuit for allowing a clock of any specified duty cycle to be created from a clock of the same frequency using standard digital delay lines. In particular, an EXOR function is implemented to generate a clock signal having a frequency which is twice the frequency of its input signals by using standard logic components such that the active branch for each input edge has an independent path to the output signal. In this manner, if a time delay is introduced into the active branch and only the active branch, the corresponding output edge and only that edge will be delayed by a like amount. Over a complete cycle of the input waveforms, four output edges are produced (two clock cycles). By varying the delay on the input branches, these output edges can be placed independently and arbitrarily within the period. As such, an output waveform having any desired duty cycle can be created independent of the phase relationship between the two input waveforms.

Circuit technique for creating predetermined duty cycle

A printed circuit board card adapted to fit into a slot and make electrical connections with cooperating terminals in the slot, the slot being disposed on the main circuit board of a personal computer system, the main circuit board including a CPU, memory, a 32-bit address bus with control signals associated therewith, and input/output circuity. The slot is coupled to the 32-bit address bus, being substantially a NUBUS bus, and the slot includes distinct identification line means which provide the slot with an identification number (distinct number) in the computer system. The card includes a decoder means which is coupled to the slot to receive the identification number; the decoder means has memory reservation means which causes 256 megabytes of memory space to be reserved for the card in the slot, such that, where the slot number is X, the 256 megabytes of reserved memory space begins at location $X000 0000 and ends at location $XFFF FFFF.

Printed circuit card with self-configuring memory system for

A clock circuit for generating two clock signals, one (CLK) having stretched clock phases on a cycle by cycle basis, and the second (2X CLK) being a clock signal having a frequency twice the frequency of the first clock signal which is phase and edge coherent with the first clock signal, including the stretched clock phases. The circuit inputs a signal generated by an oscillator which is twice the frequency of the CLK signal which is then used to generate the CLK signal for use by a microprocessor, either phase of which can be stretched on demand, while the second 2X CLK signal remains phase coherent with the microprocessor CLK signal.

Circuit for generating stretched clock phases on a cycle by cycle basis

A personal computer system includes a main circuit board having a central processing unit and expansion slots each of which is adapted to receive a printed circuit board card. The main circuit board further includes memory, a 32-bit address bus with control signals associated therewith, and input/output circuitry. The slot is coupled to the 32-bit address bus, which is substantially a NUBUS bus, and the slot includes distinct identification line means which provide the slot with an identification number (distinct number) in the computer system. The computer system reserves 256-megabytes of memory space ranging from location $X000 0000 to location $XFFF FFFF for memory on a card in a slot having a distinct number equal to $X.

Computer system for automatically reconfigurating memory space to avoid

A printed circuit board card adapted to fit into a slot and make electrical connections with cooperating terminals in the slot, the slot being disposed on the main circuit board of a personal computer system, the main circuit board including a CPU, memory, a 32-bit address bus with control signals associated therewith, and input/output circuitry. The slot is coupled to the 32-bit address bus, being substantially a NUBUS bus, and the slot includes distinct identification line means which provide the slot with an identification number (distinct number) in the computer system. The card includes a decoder means which is coupled to the slot to receive the identification number; the decoder means has memory reservation means which causes 256 megabytes of memory space to be reserved for the card in the slot, such that, where the slot number is X, the 256 megabytes of reserved memory space begins at location $X000 0000 and ends at locations $XFFF FFFF.

Growing community of inventors

Cupertino, CA, United States of America

Jonathan M Fitch