Graphcore Limited

Broadcom Corporation

Jonathan Louis Ferguson

Simon Christian Knowles

Alan Graham Alexander

Mrudula Gore

A processing unit having a register file includes: a plurality of registers each having a write enable input configured to receive a write enable signal and a write data input connected to a write data path of the processing unit and configured to write data values from the write data path for storage in a register when the write enable signal is asserted; write circuitry configured in a normal mode of operation to assert the write enable signal of a respective one of the registers to cause operational data values to be written to that register from the write data path; and data cleansing circuitry configured to control a data cleansing mode in which write enable signals of all registers in the register file are simultaneously asserted to cause cleansing data values to be simultaneously written to all registers in the register file from the write data path.

Clearing register data using a write enable signal

A processor is disclosed including: a barrel-threaded execution unit for executing concurrent threads, and a repeat cache shared between the concurrent threads. The processor's instruction set includes a repeat instruction which takes a repeat count operand. When the repeat cache is not claimed and the repeat instruction is executed in a first thread, a portion of code is cached from the first thread into the repeat cache, the state of the repeat cache is changed to record it as claimed, and the cached code is executed a number of times. When the repeat instruction is then executed in a further thread, then the already-cached portion of code is again executed a respective number of times, each time from the repeat cache. For each of the first and further instructions, the repeat count operand in the respective instruction specifies the number of times to execute the cached code.

Repeat instruction for loading and/or executing code in a claimable repeat cache a specified number of times

Computer-implemented method and system for generating an optimized description of an arithmetic function comprising at least two of an addition, a multiplication, and a rounding operation to be carried out on a plurality of data bits in a plurality of registers of an electronic circuit, the method comprising the steps: obtaining a first description of the arithmetic function; decomposing the first description to obtain a second description comprising individual binary and logical operations on data bits, wherein the data bits are arranged to their proper place value, the second description being substantially arithmetically equivalent to the first description; obtaining a third description by parallelizing at least two of the binary and logical operations on the data bits in the second description; providing a forth description comprising operations for each data bit comprised in the third description in a hardware description language as the optimized description of the electronic circuit.

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Bristol, United Kingdom

Jonathan Louis Ferguson