National Semiconductor Corporation

Jonathan Levy

Ohad Falik

Avi Mendelson

Gideon Intrater

Chaim Bendelac

Gadi Erlich

Dan Biran

Danny Hendler

A coprocessor performs an overhead function of a Java virtual machine executing in a main processor. The coprocessor includes memory access circuitry configured to access a memory also accessible by the host processor. Pointer receiving circuitry is configured to receive at least one pointer to data in the memory pertinent to the overhead function. Function performing circuitry is configured to perform the overhead function to operate on the data in the memory pointed to by the at least one pointer. Result passing circuitry configured to pass a result back to the main processor. For example, overhead functions that may be performed by the coprocessor include bytecode verification, just-in-time compiling and garbage collection.

Method for accelerating java virtual machine bytecode verification, just-in-time compilation and garbage collection by using a dedicated co-processor

A processor core for provides a linear extension of addressable memory space of a microprocessor with minimal additional hardware and software complexity. A N+x bit pointer register (e.g. program counter) holds an N+x bit instruction address. The N+x bit instruction address provides to an execution unit a pointer to an instruction in the memory to be processed by the execution unit. An encoder encodes the N+x bit address into an N bit encoding of the N+x bit address. The processor core can thereby address 2.sup.x times more memory locations than 2.sup.N. Two other registers each hold a portion of an data address (i.e. a pointer to a datum in memory to be operated on). An address former concatenates the portions of the address in the two registers to form the data address. Therefore, the address is formed from portions of the data address stored in multiple registers without performing any arithmetic on the portions.

Processor core which provides a linear extension of an addressable

A technique for generating real-time events (control signal state changes) in a TDMA (Time Division Multiple Access) wireless digital communications system integrates the functions of a Burst Mode Controller (BMC) and a microcontroller onto a single chip, organizing them such that the BMC's 'frame program' (defining time slot and bit times for real-time events) shares an instruction ROM with the microcontroller. An automatic DMA mechanism within the BMC retrieves event definitions from within the frame program and effects the real-time events defined therein at the appropriate time. The technique permits any combination of signals to be changed at any time, while simultaneously reducing overall chip area, microcontroller overhead, power-consumption and cost.

Generating real-time events in a TDMA digital wireless communications

Data in the form of a sequence of data bits is compressed by separating the data into groups of data bits. A value is derived for the respective groups from the data contained therein. When a group has a derived value equal to the derived value of at least its adjacent group, a pre-assigned control code is used as compressed data. Such compressed data is representative of the data in consecutive groups of data having the same derived value.

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Kfar-Saba, Israel

Jonathan Levy