Synopsys, Inc.

Cadence Design Systems, Inc.

Jonathan Lee Sanders

Donald John Oriordan

Salem Lee Ganzhorn

Barry Andrew Giffel

Friedrich Gunter Kurt Sendig

Hsiang-Wen Jimmy Lin

Donald John O'Riordan

Ramani Pichumani

Guy Morency

Gajanan Madhukarrao Joshi

Ruben Grigoryan

Hui Xu

Yevgenia Murad Beglaryan

Liana Badalyan

The independent claims of this patent signify a concise description of embodiments. Roughly described, disclosed is technology for yield improvement of an integrated circuit device implementing a circuit design which includes, in a first verification, verifying adherence of the circuit design to a set of performance specifications, over a first set of test cases which include variations in a fabrication process variable or an environmental condition. The verification includes identifying, for each test case of the first set of test cases, an extent to which the circuit design satisfies one or more of the performance specifications of the set of performance specifications. A second circuit design is then developed to address corner cases identified in the first verification, and the second circuit design is then re-verified using only a subset of test cases having test cases fewer than test cases of the first set of test cases.

Extreme cases sampling method for improved variation-aware full custom design

Systems and method for generating graphical visualizations of an integrated circuit (IC) design may comprise configurations for generating interactive graphical visualizations of the IC design configured for providing informative overlays to the graphical visualizations based on a selected zoom level of the graphical visualization. In certain embodiments, the graphical overlays may be generated over corresponding objects for providing information regarding hierarchies of objects, or for generating perceptible overlays over objects regardless of a zoom level of the interactive graphical visualization.

Hierarchical dynamic heat maps in full custom EDA applications

Embodiments relate to designing of integrated circuits using generation and instantiation of circuit stencils. The circuit stencil represents an abstracted version of the circuit segment. The circuit stencils include collapsed versions of the connectivity information of components and nodes of the integrated circuit. The collapsed version of the connectivity information is generated by analyzing functionality of the circuit segment and removing or replacing at least one redundant component or node of the circuit segment without modifying the functionality. The circuit stencil is used for instantiating or referencing components into a second integrated circuit.

Integrated circuit design using generation and instantiation of circuit stencils

A selection of a source testbench is received from a user. The source testbench includes a description of one or more source parameters, a description of one or more source measurements, and a plurality of source entries, each of the source entries including a value for each of the one or more source parameters and each of the one or more source measurements. Furthermore, a selection of a destination testbench is received. The destination testbench includes a description of one or more destination parameters and a plurality of destination entries including a value for each of the one or more destination parameters. One or more source entries are matched with a destination entry. One or more source measurements of the matched one or more source entries are aggregated based on an aggregation function, and the aggregated source measurements are mapped to the matched source entry.

Testbench chaining for multiple blocks in hierarchical circuit design

A method to produce a reverse skip list data structure in a computer readable medium, comprising: inputting streamed data to packets created in a temporary memory so as to create a sequence of packets; upon completion of creation of a packet in the stream, transferring the completed packet from the temporary memory to persistent memory; providing each of a plurality of respective packets with a respective pointer that skips over at least one other packet in the packet sequence and that indicates a location in persistent memory of a different respective packet in the packet sequence that was transferred to persistent memory prior to such providing of the respective pointer.

Management of very large streaming data sets for efficient writes and reads to and from persistent storage

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Santa Clara, CA, United States of America

Jonathan Lee Sanders