Semtech Corporation

Jonathan Lamb

Wolfgang Bruchner

Richard James Lansdowne

Andrew McKnight

David John Tonks

A phase detector and signal locking system controller for use in a digital phase-locked loop (PLL) application includes a first and a second phase detector where the first phase detector result is used to control the initial pull-in and the second phase detector is used to control fine tuning once the phase differences are too small for appropriate detection by the first phase detector. A post processing and control unit operates to effectively merge the two phase detector outputs and to apply the appropriate gain factor that can be used to control a PLL system.

Phase detector and signal locking system controller

A pipelined processor such as an averaging filter including at least one subtractor section and at least one adder section. Both of the subtractor section and the adder section have a plurality of adder logic units. In comparison to the conventional processor, the processor of the present invention is streamlined by the application of one or more of three techniques. First, there is the interleaving approach where the subtractor section and the adder section are interleaved with one another. Second, there is the one delay feedback approach where the adder section includes a one delay feedback for each of the adder logic units. Third, there is the delay enable signal output approach where the averaging filter includes a delay enable signal output for each of the adder logic units of the adder section.

Method and apparatus for increasing processing performance of pipelined averaging filters

A clock synthesizer produces an output clock that has a programmable phase offset from the input clock. The clock synthesizer includes an accumulator and an offset adder. The output clock is derived from the offset adder. The offset adder receives a value derived from the accumulator and a selected phase offset value. The phase difference between the non-aligned output clock and the aligned output clock is determined by the phase offset value. The time resolution of the clock synthesizer may be defined by the clock rate of the system and the number of bits used in the offset adder and the accumulator.

Method and apparatus for controlling the phase of the clock output of a digital clock

A phase detection system allows the capture range, lock range and jitter tolerance to be extended beyond &plusmn;360&deg;. The capture range for the phase detection system may be extended in programmable amounts up to several thousand clock cycles or can be set to any desired maximum capture range in steps of approximately 360&deg;. The phase detection system circuit utilizes a coarse phase detector and a fine phase detector. The phase detection system uses the digital cycle slip counter phase detector to provide a wide phase capture and lock range for a large jitter tolerance. The phase detection system combines this detector with a fine phase measurement from a PFD (phase and frequency detector) for very accurate phase control and low output jitter. The PFD operates in the approximately &plusmn;540&deg; range and provides overlap in response with a coarse phase detector using a digital cycle counter approach. The PFD allows the digital counter, used for coarse cycle slip tracking, to precondition the PFD so that the coarse and fine detectors work together with no dead-band and no conflict in responses.

Method and apparatus for increasing capture range and jitter tolerance in phase detection circuits

An improvement to a phase and frequency detector (PFD) employs an additional reset control that acts to effectively reset the registers that generate the phase indicator signals if an undesirable preconditioned state has been entered. The additional reset control signal is generated by a register that is enabled upon detection of the preconditioned state. The new reset control signal is activated upon detection of a synchronizing signal, that is based on an input source signal, while the enable control is active. The improved detector can allows a phase locked loop (PLL) system locking to the nearest input reference clock edge and it can provide immunity to missing input clock edges.

Phase and frequency detector providing immunity to missing input clock pulses

A clock output controller using a digital frequency synthesis minimizes the clock output disturbance due to input reference signal switchover. The controller includes a first and a second accumulator where the Most Significant Bit (MSB) of the first accumulator output generates the clock output signal and the MSB of the second accumulator generates a feedback signal. A reset control signal is generated by the transition edge detector/switchover controller and it is coupled to the register block of the second accumulator in order to reset the feedback signal at an appropriate time so as to match the phase of the new reference signal. A hold control signal is also generated to keep the clock output locked on the old reference signal until the feedback signal is locked to the new signal. The hold signal is then reset once locking to the new reference signal is accomplished and the clock output is fully switched over with minimal disturbance.

Reference signal switchover clock output controller

A slave clock generation system and method suitable for use with synchronous telecommunications networks generates one or more slave clocks from a selected reference clock using a direct digital synthesis technique. A multiplexer selects a reference clock from a number of available sources, each of which can be at its own spot frequency, based on a predetermined selection order. Toggle detectors monitor each of the available clock sources, and block the selection of any that are not within a specified frequency range. A local oscillator establishes short-term and long-term measurement periods; the cycles of the selected reference clock are counted over consecutive short-term measurement periods to determine the relative frequency of the selected clock with respect to the frequency of the local oscillator. The cycle counts are fed to a phase-to-clock converter, which produces a slave clock output having a frequency that varies with the relative frequency measured for the selected clock. Rounding errors are countered by monitoring both the generated slave clock and the selected reference clock over a long-term measurement period, with the difference between these two cycle counts used in a feedback path to correct the output frequency. The invention's mostly-digital implementation improves its noise-rejection and suppression characteristics, and enables the system to be integrated on a common substrate.

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Ringwood, United Kingdom

Jonathan Lamb