Freescale Semiconductor,inc.

Other

Jonathan L Cobb

Bich-Yen Nguyen

Mehul D Shroff

Mark Douglas Hall

Wei E Wu

Kevin D Lucas

Bernard J Roman

Yeong-Jyh Tom Lii

John M Grant

James Edward Vasek

Jinmiao James Shen

Anna M Phillips

William Louis Wilkinson

William D Darlington

Brian J Fisher

Vikas R Sheth

Al T Koh

Andrea Franke

Described herein are improved systems and methods for provisioning of private computer networks and application software as well as providing private SaaS.

Private network and application provisioning system

Systems and methods for overcoming technical problems associated with virtual private networks and application provisioning systems to provide ways for end-users and/or providers to control access, use, and communications associated with websites, online applications, and online services. Such systems and methods leverage techniques analogous to technologies known for implementing man-in-the-middle (MITM) attacks.

Virtual private network application platform

A photolithographic mask is adapted for use in imparting a pattern to a substrate. The pattern comprises a plurality of features. At least one of the plurality of features () is implemented in the mask as a phase shifting structure () with a unitary layer of opaque material () disposed thereon. The mask is utilized to impart the pattern to a layer over a semiconductor substrate.

Cr-capped chromeless phase lithography

A method for reducing line edge roughness (LER) in a layer of photoresist is provided. In accordance with the method, a layer of photoresist is applied to a substrate. The layer of photoresist is then patterned and annealed in an atmosphere comprising at least one gas selected from the group consisting of hydrogen, nitrogen and fluorine-containing materials. Preferably, the anneal is performed after patterning the photoresist, but either immediately after, or subsequent to, the trim.

Treatment for reduction of line edge roughness

Photoresist on a wafer is exposed using tiles on a mask that improve flare performance. Features that are not to be exposed on the photoresist correspond to features on the mask. The various features are surrounded by other features that vary and thus affect flare differently. Selected features have tiles added nearby but also far enough away to improve uniformity in the effects of flare on the various features that are intended to be present in the photoresist. The tiles are made either very small in width or partially absorbing so that the tiles are not resolved in the photoresist. Thus the tiles reduce flare but do not alter the desired pattern in the photoresist.

Non-resolving mask tiling method for flare reduction

A method of forming a semiconductor device so as to provide the device inverted isolation trenches with convex sidewalls. Initially, a plurality of composite isolation posts () are formed on a substrate () through successive deposition, lithography, and etching steps. The posts comprise a bottom layer () of silicon dioxide and an overlying etch-stop layer of silicon nitride (). An insulating material () is then deposited over the isolation posts and areas of the substrate. Isolation structures () are established by etching the insulating material to form convex sidewall spacers () at the vertical walls of the isolation posts. Active areas () between spacers are filled with semiconductor material. In an embodiment, a strained cap layer () may be imposed on the active areas. The strained cap layer has a lattice constant that is different from the lattice constant of the semiconductor material.

Inverted isolation formed with spacers

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Austin, TX, United States of America

Jonathan L Cobb