Hewlett-packard Development Company, L.p.

Microsoft Technology Licensing, LLC

Institute for the Development of Emerging Architectures, L.l.c.

Idea Corporation

Intel Corporation

Hewlett-packard Company

Other

Hewlett Packard Enterprise Development LP

Hewlett-packard Development, L.p.

Institute for the Development of Emerging Architecture L.l.c.

Idea Corporation of Delaware

Jonathan Kent Ross

Dale Calvin Morris

Achmed Rumi Zahir

Gary N Hammond

Stephen G Burger

Christophe De Dinechin

James O Hays

Koichi Yamada

William R Bryg

Todd J Kjos

Carol Linda Thompson

Cary Allen Coutant

Sunil Saxena

Robert Allen Shearer

Rajiv Gupta

Kushagra V Vaid

Jerome C Huck

Amy L Santoni

Elene Terry

John M Kessenich

Jork Loeser

Hin L Leung

Raymond Kirk Price

Karen Lee Noel

Ralph Michael Kling

Donald Charles Soltis, Jr

Eric R Delano

Leith L Johnson

Rohit Bhatia

Ronald Aigner

Tolga Ozguner

Matthew B Lovell

Vishal Jain

Jack D Mills

Prasad A Raje

Joe Perry Cowan

Teague Curtiss Mapes

Christopher Philip Ruemmler

James M Hull

Stefan M Freudenberger

William R Greene

Jay Shih Tsao

Preetika Jain

Cary Coutant

Jim Hays

Jan Simon Rellermeyer

Gary N Hammon

Carol Thompson

Matthew B Hewlett-Packard Company Lovell

The present disclosure relates to systems, methods, and computer-readable media for facilitating efficient retrieval of diagnostic information from a computing endpoint that experiences a failure condition. For example, systems described herein may detect or otherwise identify a failure condition associating with the computing endpoint operating in an erroneous or unpredictable matter. Systems described herein may involve carving out a portion of memory on the computing endpoint that is accessible to a host system (e.g., a CPU). Systems described herein may further provide a discoverable resource that enables a host system to identify and collect the diagnostic data in response to identifying a failure condition in an efficient manner and without requiring that the computing endpoint be capable of responding to data requests.

Retrieving diagnostic information from a PCI express endpoint

A system for three-dimensional imaging includes a plurality of three-dimensional imaging cameras. A first camera and a second camera may have integration times that are interleaved with the readout time of the other camera to limit interference while increasing framerate and throughput.

Systems and methods for interleaving multiple active camera frames

Input power sequencing implementations for electronic, processing, and computing systems are presented herein. In one example, a method of providing power to operational elements of an electronic system is provided. The method includes maintaining sequencing information for the operational elements that indicates relative priorities and inrush delays for each of the operational elements. Responsive to ones of the operational elements requesting transition to a powered state, the method includes placing at least indications of the ones of the operational elements into a queue, establishing a power sequencing process for servicing the queue based at least on the sequencing information associated with the operational elements in the queue, and initiating the power sequencing process to provide input power to the operational elements in the queue.

Prioritized sequencing of device inrush current

An interrupt controller includes a fabric slave that can receive MMIO operation requests, a plurality of output interrupt lines, a plurality of interrupt registers with each interrupt register corresponding to an output interrupt line, a MMIO routing circuit in communication with the fabric slave and the interrupt registers, a plurality of input interrupt lines for receiving line interrupts, and a line interrupt routing circuit in communication with the input interrupt lines and the interrupt registers. The interrupt registers store data for an interrupt that serves as an indication of the source of the interrupt and/or what task(s) need to be done for the interrupt.

Interrupt controller

A timing control system includes one or more device processors operatively coupled to one or more devices, a counter connected to the device processor(s), and a plurality of timing registers operatively coupled to the counter, each of the timing registers configured to store a value indicating a time at which an event is to be initiated at a corresponding one of the device(s). The system also includes a pulse generator operatively coupled to the counter and the timing registers, the pulse generator configured to generate one or more associated general-purpose input/output (GPIO) output signals, and send to each of the one or more devices an associated GPIO output signal to initiate the event at a plurality of the one or more devices in coordination with one another or to initiate the event at one of the one or more devices in coordination with another event at that device.

Low-latency timing control

A data processor includes a redirection dynamic address redirection table (DART) for redirecting instruction fetches from an original memory location with an original address to a target memory location with a target address.

In-processor dynamic address redirection table for substituting instruction strings

Access to a shared resource by a plurality of execution units is organized and controlled by issuing tickets to each execution unit as they request access to the resource. The tickets are issued by a hardware atomic unit so that each execution unit receives a unique ticket number. A current owner field indicates the ticket number of the execution unit that currently has access to the shared resource. When an execution unit has completed its access, it releases the shared resource and increments the owner field. Execution units awaiting access to the shared resource periodically check the current value of the owner field and take control of the shared resource when their respective ticket values match the owner field.

Controlling access to shared resource by issuing tickets to plurality of execution units

A technology can be provided for managing shared memory used by a plurality of compute nodes. An example system can include a shared globally addressable memory to enable access to shared data by the plurality of compute nodes. A memory interface can process memory requests sent to the shared globally addressable memory from the plurality of processors. A memory write module can be included for the memory interface to allocate memory locations in the shared globally addressable memory and write read-only data to the globally addressable memory from a writing compute node. In addition, a read module for the memory interface can map read-only data in the globally addressable shared memory as read-only for subsequent accesses by the plurality of compute nodes.

Managing shared memory used by compute nodes

A system and corresponding method virtualizes a real-time clock in the presence of a time-disrupting event. The real-time clock is used with physical machines and includes a single time source within each of the physical machines. The system is implemented in one or more programmable devices, which may be hardware and/or software devices, or a combination of hardware and software devices. The physical machines include one or more virtual machines. The system includes an offset module that determines a time difference offset between a virtual interrupt timer counter (ITC) associated with a virtual machine and a physical interrupt timer counter (ITC) associated with a physical machine. The system also includes a virtual machine monitor that computes one or more first time adjustments based on the offset and applies the adjustments to eliminate at least a first part of the offset.

System and method for gradually adjusting a virtual interval timer counter value to compensate the divergence of a physical interval timer counter value and the virtual interval timer counter value

A processor chip may have a built-in hardware lock and deterministic exclusive locking of the hardware lock by execution units executing in parallel on the chip. A set of software locks may be maintained, where the execution units set and release the software locks only by first acquiring a lock of the hardware lock. A first execution unit sets a software lock after acquiring a lock of the hardware lock, and other execution units, even if exclusively locking the hardware lock, are unable to lock the software lock until after the first execution unit has reacquired a lock of the hardware lock and possibly released the software lock while exclusively locking the hardware lock. An execution unit may release a software lock after and while holding a lock of the hardware lock. The hardware lock is released when a software lock has been set or released.

Hierarchical software locking

Embodiments of apparatuses and methods for improving performance in a virtualization architecture are disclosed. In one embodiment, an apparatus includes a processor and a processor abstraction layer. The processor abstraction layer includes instructions that, when executed by the processor, support techniques to improve the performance of the apparatus in a virtualization architecture.

Performance in a virtualization architecture with a processor abstraction layer

In one embodiment of the present invention, a virtual-machine monitor detects entry and exit from guest-operating system code, storing the values of a set of high-order floating point registers in memory on entry, and restoring the values of the set of high-order floating point registers on exit. The virtual-machine monitor can then use the set of high-order floating point registers as scratch registers for emulation of guest-operating-system instructions. In alternative embodiments, a virtual-machine monitor obtains scratch registers for any code that the virtual-machine monitor can detect entry into and exit from, and for which a set of infrequently used registers can be identified, by storing the current contents of the set of registers upon detected entry into the code and restoring the original contents of the set of registers upon exit from the code.

Method for providing scratch registers for use by a virtual-machine monitor

Various embodiments of the present invention are directed to efficient methods by which virtual-machine monitors can introduce instructions into guest-operating-system code. In one embodiment of the present invention, the virtual-machine monitor builds instructions dynamically, at insertion time, using specified values for fields within the instruction. In one embodiment of the present invention, the instructions and instruction field values are stored in an instruction-block-representing data structure.

Method and system for replacing instructions and instruction blocks in computer code

A technique to improve the performance of virtualized input/output (I/O) resources of a microprocessor within a virtual machine environment. More specifically, embodiments of the invention enable accesses of virtualized I/O resources to be made by guest software without necessarily invoking host software. Furthermore, embodiments of the invention enable more efficient delivery of interrupts to guest software by alleviating the need for host software to be invoked in the delivery process.

Technique to virtualize processor input/output resources

A method for mapping an active entry within a virtually hashed page table is disclosed. An active entry within a virtually hashed page table is populated. A link table for locating a link at an offset from an active entry is maintained. This link table continues to be maintained as a valid link table until an occupied head bucket threshold is exceeded or a collision has occurred.

Mapping an active entry within a hashed page table

Growing community of inventors

Woodinville, WA, United States of America

Jonathan Kent Ross