Intel Corporation

Jonathan Kenny

Debra Bernstein

William G Burroughs

Niall D McDonnell

Hugh Wilkinson

Andrew Cunningham

Tsung-Yuan Charles Tai

Ren Wang

Andrew J Herdrich

John Joseph Browne

Jr-Shian Tsai

Timothy Verrall

David Sonnier

Stephen R Van Doren

Yipeng Wang

Michael J McGrath

Bruce Richardson

James T Clee

Narender R Vangati

Christopher MacNamara

Jerry Pirog

Maryam Tahhan

Joseph R Hasting

Te Khac Ma

Sean Harte

Gage Eads

Kevin Devey

Stephen Miller

An Yan

Jamison D Whitesell

Edwin Verplanke

Bradley A Burres

Namakkal N Venkatesan

A computing apparatus, including: a hardware platform; and an interworking broker function (IBF) hosted on the hardware platform, the IBF including a translation driver (TD) associated with a legacy network appliance lacking native interoperability with an orchestrator, the IBF configured to: receive from the orchestrator a network function provisioning or configuration command for the legacy network appliance; operate the TD to translate the command to a format consumable by the legacy network appliance; and forward the command to the legacy network appliance.

Interworking of legacy appliances in virtualized networks

Techniques and apparatus for processor queue management are described. In one embodiment, for example, an apparatus to provide queue congestion management assistance may include at least one memory and logic for a queue manager, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine queue information for at least one queue element (QE) queue storing at least one QE, compare the queue information to at least one queue threshold value, and generate a queue notification responsive to the queue information being outside of the queue threshold value. Other embodiments are described and claimed.

Techniques for processor queue management

Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache ('LLC'), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.

Multi-core communication acceleration using hardware queue device

Technologies for a distributed hardware queue manager include a compute device having a processor. The processor includes two or more hardware queue managers as well as two or more processor cores. Each processor core can enqueue or dequeue data from the hardware queue manager. Each hardware queue manager can be configured to contain several queue data structures. In some embodiments, the queues are addressed by the processor cores using virtual queue addresses, which are translated into physical queue addresses for accessing the corresponding hardware queue manager. The virtual queues can be moved from one physical queue in one hardware queue manager to a different physical queue in a different physical queue manager without changing the virtual address of the virtual queue.

Technologies for a distributed hardware queue manager

Growing community of inventors

Galway, Ireland

Jonathan Kenny