Intel Corporation

Jonathan Kennedy

Joydeep Ray

Abhishek R Appu

Travis T Schluessler

Prasoonkumar Surti

Altug Koker

Ankur N Shah

Karthik Vaidyanathan

Atsuo Kuwahara

Nikos Kaburlasos

Jeffery S Boles

John H Feit

Jacek Kwiatkowski

Balaji Vembu

Hugues Labbe

Murali Ramadoss

Michael Apodaca

Sameer Kp

Adam T Lake

Slawomir Grajewski

Kiran Chand Veernapu

Abhishek Venkatesh

Gabor Liktor

Narayan Biswal

Stanley J Baran

James M Holland

Gokcen Cilingir

Nilesh V Shah

Barnan Das

Archie Sharma

Mayuresh M Varerkar

Louis Feng

Eric J Hoekstra

Subramaniam M Maiyuran

Vasanth Ranganathan

Kamal Sinha

Kai Xiao

Devan Burke

Mohammed Tameem

Elmoustapha Ould-Ahmed-Vall

Carsten Benthin

Tomer Bar-On

Chandrasekaran Sakthivel

Wenyin Fu

Bhushan M Borole

Guei-Yuan Lueh

David M Puffer

Supratim Pal

Andrew T Lauritzen

David M Cimini

Jianfang Olena Zhu

Bo Qiu

Kim Pallister

Gang Y Chen

Joy Chandra

Deepak Gandiga Shivakumar

Hong Bin Liao

Nikhil Talpallikar

Ajit Krisshna Nandyal Lakshman

Anand Srivatsa

Ananda V Kommaraju

Cristiano J Ferreira

Brandt M Guttridge

Frank J Soqui

Sanjeev S Jahagirdar

Justin E Gottschlich

Anbang Yao

John Charles Weast

Eriko Nurvitadhi

Sara S Baghsorkhi

Xiaoming Chen

Nadathur Rajagopalan Satish

Liwei Ma

Farshad Akhbari

Kevin Nealis

Jeremy Bottleson

Sameer K P

Gang Chen

Jeffrey S Boles

Described herein are various embodiments of reducing dynamic power consumption within a processor device. One embodiment provides a technique for dynamic link width adjustment based on throughput demand for client of an interconnect fabric. One embodiment provides for a parallel processor comprising an interconnect fabric including a dynamically configurable bus widths and frequencies.

Interconnect fabric link width reduction to reduce instantaneous power consumption

Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.

Controlling coarse pixel size from a stencil buffer

An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.

Motion biased foveated renderer

Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.

Processor power management

Systems, apparatuses and methods may provide away to render augmented reality (AR) and/or virtual reality (VR) sensory enhancements using ray tracing. More particularly, systems, apparatuses and methods may provide a way to normalize environment information captured by multiple capture devices, and calculate, for an observer, the sound sources or sensed events vector paths. The systems, apparatuses and methods may detect and/or manage one or more capture devices and assign one or more the capture devices based on one or more conditions to provide observer an immersive VR/AR experience.

Augmented reality virtual reality ray tracing sensory enhancement system, apparatus and method

In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

Dynamic distributed training of machine learning models

Systems, apparatuses, and methods may provide for technology to process graphics data in a virtual gaming environment. The technology may identify, from graphics data in a graphics application, redundant graphics calculations relating to common frame characteristics of one or more graphical scenes to be shared between client game devices of a plurality of users and calculate, in response to the identified redundant graphics calculations, frame characteristics relating to the one or more graphical scenes. Additionally, the technology may send, over a computer network, the calculation of the frame characteristics to the client game devices.

Cloud based distributed single game calculation of shared computational work for multiple cloud gaming client devices

An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The system may include one or more of a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls, a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode, a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage, and an order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage. Other embodiments are disclosed and claimed.

Order independent asynchronous compute and streaming for graphics

Described herein are various embodiments of reducing dynamic power consumption within a processor device. One embodiment provides a technique for dynamic link width reduction based on throughput demand for client of an interconnect fabric. One embodiment provides for a parallel processor comprising an interconnect fabric including a dynamically configurable bus widths and frequencies.

An apparatus to facilitate control flow in a graphics processing system is disclosed. The apparatus includes logic a plurality of execution units to execute single instruction, multiple data (SIMD) and flow control logic to detect a diverging control flow in a plurality of SIMD channels and reduce the execution of the control flow to a subset of the SIMD channels.

Control flow mechanism for execution of graphics processor instructions using active channel packing

Systems, apparatuses and methods may provide away to render augmented reality and virtual reality (VR/AR) environment information. More particularly, systems, apparatuses and methods may provide a way to selectively suppress and enhance VR/AR renderings of n-dimensional environments. The systems, apparatuses and methods may deepen a user's VR/AR experience by focusing on particular feedback information, while suppressing other feedback information from the environment.

Augmented reality and virtual reality feedback enhancement system, apparatus and method

The systems, apparatuses and methods may provide a way to adaptively process and aggressively cull geometry data. Systems, apparatuses and methods may provide for processing, by a positional only shading pipeline (POSH), geometry data including surface triangles for a digital representation of a scene. More particularly, systems, apparatuses and methods may provide a way to identify surface triangles in one or more exclusion zones and non-exclusion zones, and cull surface triangles in one or more exclusion zones.

Positional only shading pipeline (POSH) geometry data processing with coarse Z buffer

Growing community of inventors

Bristol, United Kingdom

Jonathan Kennedy