Motorola Corporation

Freescale Semiconductor,inc.

Other

Jonathan K Abrokwah

Matthias Passlack

Zhiyi Jimmy Yu

Jenn-Hwa Huang

Corey D Overgaard

Mariam G Sadaka

Ravindranath Droopad

William J Ooms

Jerald A Hallmark

Rodolfo Lucero

Brian Bowers

Lianjun Liu

Darrell Glenn Hill

Carl Lynn Shurboff

Jeffrey A Rollman

Herbert Goronkin

Bruce A Bernhardt

Jun J Wang

Olin L Hartin

Majid M Hashemi

X Theodore Zhu

Qiang Li

Jaeshin Cho

Saied N Tehrani

Mark A Durlam

Vijay K Nair

Daniel S Marshall

Kelly Wayne Kyler

Peter Zurcher

Schyi-Yi Wu

Stephen P Rogers

Jason R Fender

Danny L Thompson

Michael P LaMacchia

Karthik Rajagopalan

Marcus R Ray

Wayne A Cronin

Terry K Daly

Haldane S Henry

James Cotronakis

Sandeep Pendharkar

Zhiguo Wang

Farideh Nikpourian

Vernon Patrick O'Neil, Ii

Iain G Thayne

Stephen B Clemens

Jimmy Z Yu

Keri L Costello

Zhiyi (Jimmy) Yu

Adolfo G Reyes

Haiping Zhou

Richard J Hill

Xu Li

David A Moran

An improved insulated gate field effect device is obtained by providing a substrate desirably comprising a III-V semiconductor, having a further semiconductor layer on the substrate adapted to contain the channel of the device between spaced apart source-drain electrodes formed on the semiconductor layer. A dielectric layer is formed on the semiconductor layer. A sealing layer is formed on the dielectric layer and exposed to an oxygen plasma. A gate electrode is formed on the dielectric layer between the source-drain electrodes. The dielectric layer preferably comprises gallium-oxide and/or gadolinium-gallium oxide, and the oxygen plasma is preferably an inductively coupled plasma. A further sealing layer of, for example, silicon nitride is desirably provided above the sealing layer. Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.

Insulated gate field effect transistors

An improved insulated gate field effect device () is obtained by providing a substrate () desirably comprising a III-V semiconductor, having a further semiconductor layer () on the substrate () adapted to contain the channel () of the device () between spaced apart source-drain electrodes () formed on the semiconductor layer (). A dielectric layer () is formed on the semiconductor layer (). A sealing layer () is formed on the dielectric layer () and exposed to an oxygen plasma (). A gate electrode () is formed on the dielectric layer () between the source-drain electrodes (). The dielectric layer () preferably comprises gallium-oxide () and/or gadolinium-gallium oxide (), and the oxygen plasma () is preferably an inductively coupled plasma. A further sealing layer () of, for example, silicon nitride is desirably provided above the sealing layer (). Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.

Method for forming an insulated gate field effect device

A balanced-unbalanced (balun) signal transformer includes an unbalanced port, a balanced port coupled to the unbalanced port, the balanced port comprising a first terminal and a second terminal, a first capacitor coupled to the first terminal, a first inductor coupled to ground and the first capacitor, a second capacitor coupled to the second terminal, and a second inductor coupled to ground and the second capacitor. The transformer may also include a third capacitor coupled to a terminal of the unbalanced port; and a third inductor coupled to the third capacitor and the third terminal.

Balun signal transformer and method of forming

According to one aspect of the present invention, a method of forming a microelectronic assembly, such as an integrated passive device (IPD) (), is provided. An insulating dielectric layer () having a thickness () of at least 4 microns is formed over a silicon substrate (). At least one passive electronic component () is formed over the insulating dielectric layer ().

Integrated passive device with a high resistivity substrate and method for forming the same

A semiconductor fabrication process includes forming a gate dielectric layer () overlying a substrate () that includes a III-V semiconductor compound. The gate dielectric layer is patterned to produce a gate dielectric structure () that has a substantially vertical sidewall (), e.g., a slope of approximately 45&#xb0; to 90&#xb0;. A metal contact structure () is formed overlying the wafer substrate. The contact structure is laterally displaced from the gate dielectric structure sufficiently to define a gap () between the two. The wafer () is heat treated, which causes migration of at least one of the metal elements to form an alloy region () in the underlying wafer substrate. The alloy region underlies the contact structure and extends across all or a portion of the wafer substrate underlying the gap. An insulative or dielectric capping layer () is then formed overlying the wafer and covering the portion of the substrate exposed by the gap.

III-V MOSFET fabrication and device

An electronic assembly includes a substrate (), a balun transformer () formed on the substrate () and including a first winding () and a second winding (), each having respective first and second ends, and a reaction circuit component () formed on the substrate () and electrically coupled to the second winding () between the first and second ends thereof. The balun transformer () and the reaction circuit component () jointly form a harmonically suppressed balun transformer having a fundamental frequency, and the reaction circuit component () is tuned such that the harmonically suppressed balun transformer resonates at a selected harmonic of the fundamental frequency.

Balun transformer with improved harmonic suppression

A radio frequency ('RF') circuit configured in accordance with an embodiment of the invention is fabricated on a substrate using integrated passive device ('IPD') process technology. The RF circuit includes at least one RF signal line section and an integrated RF coupler located proximate to the RF signal line section. The integrated RF coupler, its output and grounding contact pads, and its matching network are fabricated on the same substrate using the same IPD process technology. The integrated RF coupler provides efficient and reproducible RF coupling without increasing the die footprint of the RF circuit.

Radio frequency circuit with integrated on-chip radio frequency signal coupler

A method of manufacturing a semiconductor component and the component thereof includes forming a dielectric layer () over a portion of a passivation ledge () in an emitter layer () and overlapping a base contact () onto the dielectric layer ().

Method of manufacturing a semiconductor component and semiconductor component thereof

A method is provided for etching quaternary interface layers of In Ga As P which are formed between layers of GaAs and InGaP in heterojunction bipolar transistors (HBTs). In accordance with the method, the interface is exposed by etching the GaAs layer with an etchant that is selective to InGaP. The interface is then etched with a dilute aqueous solution of HCl and H O that is selective to InGaP. The controlled etching provided by this methodology allows HBTs to be manufactured with more sophisticated, near ideal designs which may contain multiple GaAs/InGaP interfaces.

Chemistry for etching quaternary interface layers on InGaAsP mostly formed between GaAs and InxGa(1-x)P layers

A method of manufacturing a semiconductor component includes forming a first capacitor electrode ( ) over a substrate ( ), forming a capacitor dielectric layer ( ) over the first capacitor electrode, and forming a second capacitor electrode ( ) over the capacitor dielectric layer. The capacitor dielectric layer is made of aluminum.

Method of manufacturing a semiconductor component having a capacitor

A method of manufacturing a semiconductor component and the component thereof includes forming a dielectric layer ( ) over a portion of a passivation ledge ( ) in an emitter layer ( ) and overlapping a base contact ( ) onto the dielectric layer ( ).

An insulator-compound semiconductor interface structure is disclosed including compound semiconductor material with a spacer layer of semiconductor material having a bandgap which is wider than the bandgap of the compound semiconductor material positioned on a surface of the compound semiconductor material and an insulating layer positioned on the spacer layer. Minimum and maximum thicknesses of the spacer layer are determined by the penetration of the carrier wave function into the spacer layer and by the desired device performance. In a specific embodiment, the interface structure is formed in a multi-wafer epitaxial production system including a transfer and load module with a III-V growth chamber attached and an insulator chamber attached.

Insulator-compound semiconductor interface structure

A gate quality oxide-compound semiconductor structure (10) is formed by the steps of providing a III-V compound semiconductor wafer structure (13) with an atomically ordered and chemically clean semiconductor surface in an ultra high vacuum (UHV) system (20), directing a molecular beam (26) of gallium oxide onto the surface of the wafer structure to initiate the oxide deposition, and providing a second beam (28) of atomic oxygen to form a Ga.sub.2 O.sub.3 layer (14) with low defect density on the surface of the wafer structure. The second beam of atomic oxygen is supplied upon completion of the first 1-2 monolayers of Ga.sub.2 O.sub.3. The molecular beam of gallium oxide is provided by thermal evaporation from a crystalline Ga.sub.2 O.sub.3 or gallate source, and the atomic beam of oxygen is provided by either RF or microwave plasma discharge, thermal dissociation, or a neutral electron stimulated desorption atom source.

Method of forming a gate quality oxide-compound semiconductor structure

A method of preparing crystalline alkaline earth metal oxides on a Si substrate wherein a Si substrate with amorphous silicon dioxide on a surface is provided. The substrate is heated to a temperature in a range of 700.degree. C. to 800.degree. C. and exposed to a beam of alkaline earth metal(s) in a molecular beam epitaxy chamber at a pressure within approximately a 10.sup.-9 -10.sup.-10 Torr range. During the molecular beam epitaxy the surface is monitored by RHEED technique to determine a conversion of the amorphous silicon dioxide to a crystalline alkaline earth metal oxide. Once the alkaline earth metal oxide is formed, additional layers of material, e.g. additional thickness of an alkaline earth metal oxide, single crystal ferroelectrics or high dielectric constant oxides on silicon for non-volatile and high density memory device applications.

Method of preparing crystalline alkaline earth metal oxides on a Si

A method of passivating the surface of a Si wafer is disclosed including the steps of cleaning the surface of the Si wafer and depositing an alkaline earth metal on the clean surface at a wafer temperature in a range of approximately 400.degree. C. to 750.degree. C. The surface is monitored during deposition to detect a (4.times.2) surface reconstruction pattern indicating approximately a one-quarter monolayer of alkaline earth metal is formed. The wafer is annealed at a temperature in a range of 800.degree. C. to 900.degree. C. until the alkaline earth metal forms an alkaline earth metal silicide with a (2.times.1) surface pattern on the surface.

Method of passivating the surface of a Si substrate

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Tempe, AZ, United States of America

Jonathan K Abrokwah